Prosecution Insights
Last updated: August 18, 2026
Application No. 18/621,195

LIQUID EJECTION APPARATUS AND PRINT HEAD

Non-Final OA §103
Filed
Mar 29, 2024
Priority
Mar 31, 2023 — JP 2023-058274
Examiner
FIDLER, SHELBY LEE
Art Unit
2853
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Seiko Epson Corporation
OA Round
3 (Non-Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
898 granted / 1136 resolved
+11.0% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
37 currently pending
Career history
1165
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
49.2%
+9.2% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
17.2%
-22.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1136 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/16/2026 has been entered. Response to Arguments Applicant’s arguments with respect to claim(s) 1 and 7 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Please see the newly applied reference to Choi et al., which teaches the functional use of protruding terminals from a bottom surface of a packaging mold member. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4-7, and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozawa et al. (US 2022/0242108 A1) in view of Madrid et al. (US 2004/0063240 A1) and Choi et al. (US 2002/0074634 A1). Regarding claims 1 and 7: Nozawa et al. disclose a liquid ejection apparatus (1) comprising a print head (head unit 2) comprising: an ejection head (print head 20) that ejects a liquid according to driving of a piezoelectric element (60: paragraph 42); a drive signal output circuit (driving circuit 50) that outputs a drive signal (COMA/COMB) for driving the piezoelectric element (paragraph 37 & Fig. 2); and a base drive signal output circuit (control unit 10) that outputs a base drive signal (reference drive signals dA/dB) that is a base of the drive signal (paragraph 25), wherein the drive signal output circuit includes: an integrated circuit (500) that receives the base drive signal (Fig. 10) and outputs a first control signal (gate signal Hgd: paragraph 81 & Fig. 10), a first switching element (transistor M1) operated by the first control signal (paragraph 81 & Fig. 10), and a wiring board (wiring substrate 55) on which the integrated circuit and the first switching element are provided (Fig. 13), and wherein the first switching element includes: a first transistor chip (“semiconductor chip ... forming a transistor element”: paragraph 124), a first terminal (terminal gt), a second terminal (at least one of terminals st1-st3), and a third terminal (at least one of terminals dt1-dt5), all of which are electrically coupled to the first transistor chip (paragraphs 125-127), and a first mold member (housing Pck) covering the first transistor chip (paragraph 124 & Figs. 11-12), wherein a conduction state between the second terminal and the third terminal is controlled according to the first control signal input to the first terminal (paragraph 117 & Fig. 10), and wherein the first terminal, the second terminal, and the third terminal are provided only at positions overlapping with the first mold member along a direction normal to the wiring board (Figs. 11-12). Nozawa et al. do not expressly disclose that, as viewed in the direction normal to the wiring board, an entirety of the first terminal, the second terminal, and the third terminal is within a planar projection of the first mold member, or that the first terminal, second terminal, and third terminal protrude with respect to a bottom surface of the first mold member in the direction normal to the wiring board. However, Madrid et al. disclose a switching element (semiconductor package 100) that includes a transistor chip (101), a first terminal (gate lead 112), a second terminal (source leads 111), a third terminal (drain leads 107), and a mold member (molding material 102), wherein the terminals are positioned such that, as viewed in a direction normal to a wiring board, an entirety of the first terminal, the second terminal, and the third terminal is within a planar projection of the mold member (paragraph 25 & Fig. 2), so as to provide a more compact package (paragraph 25). Moreover, Choi et al. disclose a semiconductor package (1000) that improves solder joint reliability (paragraphs 17, 52) by utilizing terminals (leads 120) that protrude with respect to a bottom surface of a first mold member (molding material 105) in a direction normal to a wiring board (board 2000: Figs. 3C-D). Therefore, before the effective filing date of invention, it would have been obvious to a person of ordinary skill in the art to modify Nozawa et al.’s switching element to provide the first, second, and third terminals in the manner taught by Madrid et al., so as to provide a more compact package. It would have been further obvious to utilize a configuration in which the first, second, and third terminals protrude with respect to a bottom surface of the first mold member, such as taught by Choi et al., so as to improve solder joint reliability of the switching element. Regarding claims 4 and 10: Nozawa et al.’s modified apparatus comprises all the limitations of claims 1/7, and Nozawa et al. also disclose that the drive signal output circuit supplies the drive signal to 500 or more piezoelectric elements (paragraph 44). Regarding claims 5 and 11: Nozawa et al.’s modified apparatus comprises all the limitations of claims 1/7, and Nozawa et al. also disclose that the integrated circuit outputs a second control signal (Lgd: paragraph 81 & Fig. 10), wherein the drive signal output circuit includes a second switching element (transistor M2) provided on the wiring board and operated by the second control signal (paragraph 81 & Fig. 10), wherein the second switching element includes: a second transistor chip (“semiconductor chip ... forming a transistor element”: paragraph 124), a fourth terminal (terminal gt), a fifth terminal (at least one of terminals dt1-dt5), and a sixth terminal (at least one of terminals st1-st3), all of which are electrically coupled to the second transistor chip (paragraphs 125-127), and a second mold member (housing Pck) covering the second transistor chip (paragraph 124 & Figs. 11-12), wherein a conduction state between the fifth terminal and the sixth terminal is controlled according to the second control signal input to the fourth terminal (paragraph 117 & Fig. 10), and wherein the fourth terminal, the fifth terminal, and the sixth terminal are provided only at positions overlapping with the second mold member along the direction normal to the wiring board (Figs. 11-12). Regarding claims 6 and 12: Nozawa et al.’s modified apparatus comprises all the limitations of claims 5/11, and Nozawa et al. also disclose that the drive signal output circuit includes a demodulation circuit (smoothing circuit 560), wherein the integrated circuit outputs the first control signal and the second control signal according to a modulation signal (Ms) obtained by modulating the base drive signal (paragraph 86 & Fig. 10), wherein the second terminal and the fifth terminal are electrically coupled to each other (Figs. 10, 13), and wherein the demodulation circuit demodulates a signal at a coupling point where the second terminal and the fifth terminal are electrically coupled to output the demodulated signals as the drive signal (Fig. 10). Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozawa et al. as modified by Madrid et al. and Choi et al., as applied to claims 1/7 above, and further in view of Kajiyama (JP H0714669). Regarding claims 2 and 8: Nozawa et al.’s modified apparatus comprises all the limitations of claims 1/7, but does not expressly disclose that the first mold member includes a direction indicating mark indicating a direction of the first switching element. However, Kajiyama disclose an electrical component (2) in which a direction indicating mark (reference mark 4) is provided so as to indicate a direction of the first switching element (paragraphs 7-11 & Figs. 1-3), so as to easily check the mounting direction by visual inspection (paragraph 11). Therefore, at the time of filing, it would have been obvious to a person of ordinary skill in the art to modify Nozawa et al.’s apparatus/head to include a direction indicating mark, such as taught by Kajiyama, on the first mold member. Claim(s) 3 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozawa et al. as modified by Madrid et al. and Choi et al., as applied to claims 1/7 above, and further in view of Asano et al. (JP 2017107961). For citations from Asano et al., please see the machine generated English translation provided. Regarding claims 3 and 9: Nozawa et al.’s modified apparatus comprises all the limitations of claims 1/7, and Nozawa et al. also disclose that the first mold member is made of resin (paragraph 124). Nozawa et al. do not expressly disclose that the resin is an epoxy resin containing glycidyl group-containing polybutadiene. However, Asano et al. disclose a method of manufacturing a high quality and highly reliable electronic component sealed and molded of epoxy resin (epoxy resin composition 3/4), wherein the epoxy resin contains glycidyl group-containing polybutadiene (as the epoxy resin (A): page 5). Therefore, at the time of filing, it would have been obvious to a person of ordinary skill in the art to utilize the epoxy resin taught by Asano et al. as Nozawa et al.’s first mold member, so as to obtain a high quality and highly reliable first switching element. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Ito et al. (US 2003/0111717 A1) disclose a relative QFN semiconductor package in which lead terminals (8) protrude with respect to a bottom surface of a package mold member (paragraphs 99-100 & Fig. 5). Communication with the USPTO Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shelby L Fidler whose telephone number is (571)272-8455. The examiner can normally be reached Monday-Friday, 8:30am - 5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. SHELBY L. FIDLER Primary Examiner Art Unit 2853 /SHELBY L FIDLER/Primary Examiner, Art Unit 2853
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Prosecution Timeline

Mar 29, 2024
Application Filed
Dec 08, 2025
Non-Final Rejection mailed — §103
Feb 04, 2026
Response Filed
Apr 01, 2026
Final Rejection mailed — §103
Jun 16, 2026
Request for Continued Examination
Jun 22, 2026
Response after Non-Final Action
Jun 26, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
93%
With Interview (+14.3%)
2y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1136 resolved cases by this examiner. Grant probability derived from career allowance rate.

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