Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Examiner Notes
Examiner cites particular paragraphs and/or columns and lines in the references as applied to Applicant’s claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Authorization for Internet Communications in a Patent Application
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Claim Objections
Claim 8 is objected to because of the following informalities: delete “and” in ll. 3. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: “patterns ;” should be “patterns;” in ll. 8. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
As per claim 1, it is indefinite because ll. 5 recites “local” memory portions and it is not clear as to what makes the memory portions “local” because “local” is a relative and subjective term and no point of reference is provided in the claim to properly determine what “local” means. For the purposes of examination, the local memory portions is interpreted to read on the appropriate cited prior art reference(s) below. Appropriate correction is required.
As per claim 8, it is indefinite because ll. 3-4 and 7 recite “the resource access patterns” and it is unclear as to whether the resource access patterns are the same or different. In other words, are the resources access patterns that are stored in the non-volatile memory then sent via the network or are some of the resource access patterns stored and the rest are sent on the network? Do the resource access patterns recited in ll. 7 refer to those recited in ll. 2 or ll. 3? For the purposes of examination, the local memory portions is interpreted to read on the appropriate cited prior art reference(s) below. Appropriate correction is required.
As per claim 10, it is rejected using the same rationale as claim 1.
As per claim 18, it is rejected using the same rationale as claim 1.
The remaining dependent claims not specifically mentioned above are also rejected by virtue of being dependent upon one of the above rejected independent claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 10-12, and 18-20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Kumar et al. (US 2020/0310993) (hereinafter Kumar).
As per claim 1, Kumar teaches a computing device for analyzing execution of an application, the computing device comprising:
a processor of a first type ([0066] processor circuitry may include any number, type, or combination of currently available or future developed devices capable of executing machine-readable instruction sets) having a non-uniform memory access (NUMA) architecture ([0025] non-uniform memory access (NUMA) optimization) comprising:
a plurality of local memory portions ([0182] a shared cache may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache); and
a plurality of processor sets sharing the plurality of local memory portions ([0182] a shared cache may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache) and configured to execute the application as units of execution ([0058] an application executed by the processor circuitry and [0157] execution units); and
a processor of a second type ([0168] many different processor implementation types) configured to:
issue commands to the processor of the first type to execute execution units of the application ([0040] migration prediction circuitry may receive one or more signals originated by one or more applications executed by the processor circuitry and [0071] one or more applications executed on or by the processor circuitry and/or graphics processor circuitry);
identify a resource access pattern for each resource accessed in one or more of the local memory portions for the units of execution ([0040] migration prediction circuitry may include an artificial intelligence inference engine to learn, detect, and/or predict common memory access patterns and therefore proactively trigger data migrations and/or evictions from the accelerator memory circuitry. The migration prediction circuitry may receive one or more signals originated by one or more application drivers. Such signals may be based on application driver policies that trigger the data migration and/or eviction from the accelerator memory circuitry); and
subsequently execute the execution units of the application, including loading resources into the local memory portions based on the identified resource access patterns ([0040] migration prediction circuitry may include an artificial intelligence inference engine to learn, detect, and/or predict common memory access patterns and therefore proactively trigger data migrations and/or evictions from the accelerator memory circuitry. The migration prediction circuitry may receive one or more signals originated by one or more application drivers. Such signals may be based on application driver policies that trigger the data migration and/or eviction from the accelerator memory circuitry).
As per claim 2, Kumar further teaches the computing device of claim 1, wherein: the subsequent execution of the execution units includes scheduling work on the plurality of processor sets such that one or more processor sets perform more frequent memory requests to the local memory portions with lower latency than memory requests to the local memory portions with higher latency ([0021]-[0022] access to an accelerator's local memory provides the highest bandwidth and lowest latency than accesses to a peer accelerator's memory and [0157] scheduler units).
As per claim 3, Kumar further teaches the computing device of claim 1, wherein the subsequent execution of the execution units includes scheduling work on the processor sets such that each processor set performs more frequent memory requests to the local memory portions closest to a corresponding processor set than to local memory portions not closest to the corresponding processor set ([0025] intelligent migration of data to be physically close to the point of use improves application performance and [0202] maintaining frequently used data proximate the point of use e.g., data used by the accelerator circuitry is maintained in the accelerator memory circuitry, advantageously reduces system latency attributable to data transfers to/from local accelerator unit memory circuitry and peer accelerator unit memory circuitry and [0157] scheduler units).
As per claim 10, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per claim 11, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 12, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 20, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Lindsley (US 2006/0150189).
As per claim 4, Kumar does not explicitly teach wherein, in response to each portion of data to be accessed for the unit of execution being in the local memory portions closest to one of the processor sets, the processor of the second type is configured to schedule the unit of execution to be executed on the one processor set.
However, Lindsley teaches wherein, in response to each portion of data to be accessed for the unit of execution being in the local memory portions closest to one of the processor sets, the processor of the second type is configured to schedule the unit of execution to be executed on the one processor set ([0040] each of the tasks is attempted to be assigned by the scheduler to the processor that is closest to a largest portion of its allocated physical memory and [0043] the scheduler determines which of the tasks to assign to the processor based on resident set size and locational information, specifically assigning the task that has a greater amount of allocated physical memory local and closest to the processor).
Lindsley and Kumar are both concerned with NUMA architectures and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of Lindsley because it would provide a way to assign tasks to the processor to which the largest portion of the physical memory allocated to the task is local. Such predictive task assignment ensures that whenever possible, the processor having as its local memory the largest portion of the physical memory allocated to a given task is assigned the task. As such, performance is maximized. This is because the processor having as its local memory the largest portion of the physical memory allocated to a given task is the processor that will more than likely require the least number of remote memory accesses to execute the task. Because this processor has as its local memory the largest portion of the physical memory allocated to the task, as compared to any other processor of the system, it will need to access the local memory of other processors the least in executing the task. The reduction in remote memory accesses by the processors of the system thus improves performance of the system as a whole.
As per claim 5, Kumar does not explicitly teach wherein in response to a portion of data to be accessed for the unit of execution being in the local memory portions closest to the one processor set and another portion of data to be accessed for the unit of execution being in one or more other local memory portions closest to another one of the processor sets, the processor of the second type schedules the unit of execution to be executed on the one processor set and the other one of the processor sets.
However, Lindsley teaches wherein in response to a portion of data to be accessed for the unit of execution being in the local memory portions closest to the one processor set and another portion of data to be accessed for the unit of execution being in one or more other local memory portions closest to another one of the processor sets, the processor of the second type schedules the unit of execution to be executed on the one processor set and the other one of the processor sets ([0044] the scheduler determines which of the tasks to assign to the processor based on resident set size and locational information, specifically assigning the task that has a greater amount of allocated physical memory local and closest to the processor and [0046] the scheduler first attempts to assign each task to the processor that is closest or local to a largest portion of the task's allocated physical memory).
Lindsley and Kumar are both concerned with NUMA architectures and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of Lindsley because it would provide a way to minimize access to remote physical memory. For instance, a first processor that is local to the sixty-megabyte portion of physical memory allocated to the task in question at most has to remotely access the forty-megabyte portion of physical memory that is local to the second processor. By comparison, a second processor that is local to the forty-megabyte portion of physical memory allocated to this task at most has to remotely access the sixty-megabyte portion of physical memory that is local to the first processor. Therefore, assigning the task to the first processor is ideal, because it is more likely minimize remote memory accesses within the multiple-processor system, assuming equal potential of remote memory access across all of the physical memory allocated to the task.
As per claim 13, it has similar limitations as claim 4 and is therefore rejected using the same rationale.
As per claim 14, it has similar limitations as claim 5 and is therefore rejected using the same rationale.
Claims 6-7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Venkatsubramanian et al. (US 2014/0281352) (hereinafter Venkatsubramanian).
As per claim 6, Kumar does not explicitly teach wherein the processor of the second type is configured to determine the resource access patterns for each unit of execution.
However, Venkatsubramanian teaches wherein the processor of the second type is configured to determine the resource access patterns for each unit of execution ([0032] observer dynamic TLB access pattern).
Venkatsubramanian and Kumar are both concerned with TLB memory accesses in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of Venkatsubramanian because it would provide for an accurate prediction of future TLB lookups to increase the number of TLB hits to speed up the execution code by eliminating the slowdown and TLB misses traditionally associated with page walk latency.
As per claim 7, Kumar does not explicitly teach wherein identifying the resource access pattern for each resource comprises performing static analysis.
However, Venkatsubramanian teaches wherein identifying the resource access pattern for each resource comprises performing static analysis ([0024] infer pattern of TLB accesses by using static code analysis and [0031] TLB access pattern can be inferred using static analysis).
Venkatsubramanian and Kumar are both concerned with TLB memory accesses in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of Venkatsubramanian because it would provide a way to facilitate a hardware-software based solution using an ISA for enabling BT-based TLB prefetching while employing methods for accurately determining, predicting, and scheduling TLB prefetching. This BT-based precise prediction of TLB lookups may increase the number of TLB hits to speed up the execution code and its workload by eliminating the slowdown and TLB misses traditionally associated with latencies offered by conventional techniques.
As per claim 15, it has similar limitations as claim 7 and is therefore rejected using the same rationale.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Davis et al. (US 2014/0075506) (hereinafter Davis) in view of Abe (US 2008/0307172).
As per claim 8, Kumar does not explicitly teach wherein the processor of the second type is configured to: store the resource access patterns in non-volatile memory and send the resource access patterns to on one or more other computing devices via a network, and the application is subsequently executed on the one or more other computing devices in the network based on the resource access patterns.
However, Davis teaches send the resource access patterns to on one or more other computing devices via a network, and the application is subsequently executed on the one or more other computing devices in the network based on the resource access patterns ([0076] applications consume services that are running in either a Remote Node or a Central Node, as determined by optimum access patterns that consider network proximity, intervening network constraints, and tolerance for latency).
Davis and Kumar are both concerned with memory accesses in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of Davis because it would provide a way of minimizing performance and communications constraints of distributed architectures by using optimum access patterns that consider network proximity, intervening network constraints, and tolerance for latency.
Kumar in view of Davis does not explicitly teach store the resource access patterns in non-volatile memory.
However, Abe teaches store the resource access patterns in non-volatile memory (abstract and [0022] store access patterns to a main memory in the nonvolatile memory area).
Abe and Kumar are both concerned with memory accesses in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of Davis in view of Abe because it would provide a way for when only certain memory access pattern causes an error, the reproducibility of the error can be improved and failure analysis through error reproduction can be made easy. Furthermore, by feeding back the memory access pattern data to memory manufacturers, the quality of the memory can be improved and it becomes possible to record and reproduce the access pattern at the time of occurrence of the error in the main memory. As a result, it is easy to reproduce the error, facilitating the failure analysis. When only certain access pattern causes the error, the reproducibility of the error can be improved and failure analysis due to failure to reproduce the error can be reduced.
As per claim 16, it has similar limitations as claim 8 and is therefore rejected using the same rationale.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Stabrawa et al. (US 2023/0008874) (hereinafter Stabrawa) in view of Abe.
As per claim 9, Kumar does not explicitly teach wherein the processor of the second type is configured to, during execution of the application: store a resource access pattern in memory and for a unit of execution, in response to a page of data in a first local memory portion being determined, from the resource access pattern, to be in a second local memory portion different than a first memory portion, performing page migration by copying the data from the first memory portion to the second memory portion.
However, Stabrawa teaches for a unit of execution, in response to a page of data in a first local memory portion being determined, from the resource access pattern, to be in a second local memory portion different than a first memory portion, performing page migration by copying the data from the first memory portion to the second memory portion ([0393] migrate data from one portion of memory to another based upon memory access patterns by copying the data from one portion of memory to another such as with NUMA page migration).
Stabrawa and Kumar are both concerned with NUMA computing architectures and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of Stabrawa because it would provide a technical solution to solve a technical problem of providing scalable primary memory to a computing system. The primary memory may scale on demand. The primary memory may be external to the computing system to solve a technical problem of efficiently using available primary memory capacity. For example, the technical solution may enable multiple clients to share a single region and/or external memory allocation when using a memory allocation interface. Alternatively, or in addition, the technical solution may enable applications that use a memory allocation interface to be migrated from one physical machine to another, without losing metadata related to allocated portions.
Kumar in view of Stabrawa does not explicitly teach store a resource access pattern in memory.
However, Abe teaches store a resource access pattern in memory (abstract and [0022] store access patterns to a main memory in the nonvolatile memory area).
Abe and Kumar are both concerned with memory accesses in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of Stabrawa in view of Abe because it would provide a way for when only certain memory access pattern causes an error, the reproducibility of the error can be improved and failure analysis through error reproduction can be made easy. Furthermore, by feeding back the memory access pattern data to memory manufacturers, the quality of the memory can be improved and it becomes possible to record and reproduce the access pattern at the time of occurrence of the error in the main memory. As a result, it is easy to reproduce the error, facilitating the failure analysis. When only certain access pattern causes the error, the reproducibility of the error can be improved and failure analysis due to failure to reproduce the error can be reduced.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of VelurEunni (US 2008/0104337) in view of Abe.
As per claim 17, Kumar does not explicitly teach storing, by the processor of the second type, a resource access pattern in memory; and for a unit of execution, in response to a page of data in a first local memory portion being determined, from the resource access pattern, to be in a second local memory portion different than a first memory portion, performing page migration by: copying the data from the first memory portion to the second memory portion; changing a virtual page to physical page mapping; and mapping a virtual address to a physical address of a new page in the second local memory portion.
However, VelurEunni teaches for a unit of execution, in response to a page of data in a first local memory portion being determined, from the resource access pattern, to be in a second local memory portion different than a first memory portion, performing page migration by: copying the data from the first memory portion to the second memory portion; changing a virtual page to physical page mapping; and mapping a virtual address to a physical address of a new page in the second local memory portion ([0033] the OS will copy data from one page to a new page. The OS then updates virtual address to physical address mapping with the new page allocated by the OS).
VelurEunni and Kumar are both concerned with memory accesses computing architectures and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of VelurEunni because it would provide a way for the resulting method to be performed locally within a node without requiring wire protocol changes to a standard RDMA protocol. Thus, the resulting system would be completely interoperable with RDMA-standards compliant devices from any vendor. The only requirement on the OS would be to perform and complete copy-on-write processing before retransmission timeouts expire on the RDMA connection. Furthermore, the system can preserve the POSIX (Portable OS Interface for UNIX) fork semantics and shared memory semantics, and does not negatively impact methods that rely on copy-on-write to achieve optimization.
Kumar in view of VelurEunni do not explicitly teach storing, by the processor of the second type, a resource access pattern in memory.
However, Abe teaches storing, by the processor of the second type, a resource access pattern in memory (abstract and [0022] store access patterns to a main memory in the nonvolatile memory area).
Abe and Kumar are both concerned with memory accesses in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kumar in view of VelurEunni in view of Abe because it would provide a way for when only certain memory access pattern causes an error, the reproducibility of the error can be improved and failure analysis through error reproduction can be made easy. Furthermore, by feeding back the memory access pattern data to memory manufacturers, the quality of the memory can be improved and it becomes possible to record and reproduce the access pattern at the time of occurrence of the error in the main memory. As a result, it is easy to reproduce the error, facilitating the failure analysis. When only certain access pattern causes the error, the reproducibility of the error can be improved and failure analysis due to failure to reproduce the error can be reduced.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Uppal et al. (US 2018/0081541) disclose memory sampling based on migrating page caches.
Tsirkin et al. (US 2023/0418649) disclose copy-less NUMA balancing hypervisor memory migration.
Tsirkin et al. (US 2016/0350260) disclose dynamic NUMA locality for remote directed memory access applications.
Stevens (US 6,289,424) disclose managing memory in a NUMA system.
James et al. (US 6,035,377) disclose determining memory pages having greatest frequency of access in a NUMA system.
Bhat et al. (US 6,769,017) disclose memory-affinity process scheduling in NUMA systems.
Accapadi et al. (US 2012/0221812) disclose preserving memory affinity in NUMA systems.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam Lee whose telephone number is (571) 270-3369. The examiner can normally be reached on M-TH 8AM-5PM.
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner’s supervisor, Pierre Vital, can be reached at the following telephone number: (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam Lee/Primary Examiner, Art Unit 2198 July 27, 2026
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