Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-5, 8, 9, 13-17 are objected to because of the following informalities:
Claims 1 and 13 disclose “a shared register allocation cache.” Dependent claims 2, 3, 14, and 15 recite “searching a shared register allocation cache.” Because the cache was already disclosed in parent claim 1 and 13, the dependent claims should recite searching the shared register allocation cache.
Claims 5 and 17 disclose “wherein allocating shared registers to the allocating task and updating a cache entry to record the allocation comprises: …” (emphasis added) that refers to the step “allocating shared registers to the allocating task and assigning a cache entry to record the allocation” (emphasis added) in parent claim 4 and 16 respectively. It is recommended to amend the phrase to change “updating” to “assigning” to resolve terminology mismatches.
Claim 8 discloses “shared resources identified in a cache entry.” Since parent claim 1 discloses “shared register allocations,” it is recommended to change “shared resources” to “shared registers.”
Claim 9 discloses “a valid bit and a cache index (and an allocation base, wherein the valid bit...” There is an opening parenthesis before “and an allocation base” It is recommended to amend the phrase to remove the opening parenthesis.
Claim 16 discloses “The shared register allocation cache according to claim 13, the shared register resource manager is arranged … “. It is missing the transition word and should disclose “The shared register allocation cache according to claim 13, wherein the shared register resource manager is arranged … ” (emphasis added).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of pre-AIA 35 U.S.C. 112, second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 12, and 18 are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 6 and 18 disclose “a counter” instead of referring back to a previously disclosed counter. For example, it recites incrementing a counter, then later decrementing a counter, and finally concludes if the counter... is zero. It is unclear if these are all the same counter or multiple different counters. If it is the same counter, subsequent references must be to “the counter.” For the purpose of examination, it is interpreted as same counter.
Claim 12 discloses “… evicting the eligible cache entry …” (line 13, emphasis added). However, the scope of limitation of is indefinite due to lack of antecedent basis. For the purpose of examination, it is interpreted as “an eligible cache entry.”
Allowable Subject Matter
Claims 1-5, 7-11, 13-17, 19, and 20 are allowed.
Claims 6, 12, and 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
The Sideris et al. (US 2023/0062386) discloses “Each thread of a group of one or more execution threads that are executing a shader program will have an associated set of registers to be used for storing data for the execution thread; Where there are plural execution units, each execution unit may have its own distinct group of registers (register file), or there may be a single group of registers (register file) shared between plural (e.g. some or all) of the separate execution units” (paragraph [0129]), “The warp manager 34 will then check if the PC 801 hits in the instruction cache 802 and gets back a link to the cache line and offset to the instruction. If it doesn't hit, the spawned thread group will wait until the instructions are loaded into the instruction cache 802” (paragraph [0223], emphasis added), and “When the instructions for the shader program that the thread group is spawned for are present in the instruction cache 802, the thread group execution controller (scheduler) 803 then issues the thread group to a processing element (execution unit) 32 to execute the instructions in the shader program (‘warp_issue’))” (paragraph [0224], emphasis added). The claim requires that a cache hit prevents the task from being issued because the allocation is already known/cached and doesn’t need to be re-calculated or re-issued to an allocator. However, Sideris discloses that a cache hit in the instruction cache is exactly what causes the thread group to be issued. Thus, Sideris cannot anticipate or render obvious a claim limitation when it explicitly teaches the exact opposite behavior.
Damani et al. (US 2023/0144553) discloses “Within the physical register file 402, some registers are allocated to particular threads (per-thread allocated registers 408). Some sets of registers are not allocated but are reserved for use by threads within particular thread blocks (intra-block reuse pool 406) … Threads not in any of these allocations or reservations are “free” and available for use by any thread that needs them” (paragraph [0072]), “[0075] For example, when a thread or warp is releasing allocated state 502 registers acquired from any one of the free state 508, inter-block reserved state 504, or intra-block reserved state 506, it may check the status of other threads or warps in its thread block to determine whether or not they need additional registers. If not, the thread or warp may issue an inter-block release instruction for the allocated state 502 registers, placing them into the inter-block reserved state 504. Otherwise the thread or warp may issue an intra-block release instruction to place the allocated state 502 registers into the intra-block reserved state 506” (paragraph [0075]), and “Here a status value of “1” indicates the register is allocated. A status or thread value of “0” indicates the register is not allocated. A value of “0” in the thread block field indicates the register is not reserved for a particular thread block” (paragraph [0080]). The cited passages disclose register allocation states and reuse behavior, not a shared register allocation cache that returns a cache-hit identifier and prevents issuance of the allocating task as required by claim.
Atluri et al. (US 2024/0118899) discloses “shared register access and use of shared memory/L1 cache by threads in a block” (paragraphs [0032] and [0138]). However, Atluri do not disclose a shared register allocation cache, cache entries indexed by a secondary program, or returning cache-hit information that prevents issuance of the allocating task.
Alexander et al. (US 2020/0210192) discloses “shared registers and reuse of code cached in a repeat cache” (paragraphs [0032]-[0034]). However, Alexander do not disclose a shared register allocation cache that stores allocation records keyed by a secondary program, nor do they disclose returning a cache-hit identifier whose effect is to prevent issuance of the allocating task
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/SISLEY N KIM/Primary Examiner, Art Unit 2196 6/8/2026
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