DETAILED ACTION
Claims 1-18, 21-22 are pending. Claims 19-20 are cancelled.
Priority: 3/29/2024
Assignee: Advanced Micro Devices
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/6/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-18, 21-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The following limitation is vague, opaque, incoherent or otherwise unclear, thereby indefinite:
…updating the plurality of cache ways to include a number of cache ways that is based on a number of die of the system which have physical memory and a number of cache ways mapped to the first physical memory of the first die, and the plurality of cache ways including a first respective cache way mapped to the first physical memory of the first die and a second respective cache way mapped to the second physical memory of the second die…
The updating function is unclear because it cannot be determined how the number of cache ways already mapped to the first die and mapped to the second die are updated. If cache ways are mapped, then they are already included in the overall system. The limitation is interpreted as integrating two die caches that have cache ways.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 11, 12, 17, 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Madan et al.(“Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy”, 2008).
As per claim 1, Madan discloses:
A system(Madan,p. 265, Fig. 1) comprising:
a first physical memory of a first die(Madan, [p. 262, Introduction, para. 4 -- The second die is composed entirely of SRAM cache banks (forming a large shared L2 cache) and employs an on-chip network so that requests from the CPU can be routed to the correct bank]);
a second physical memory of a second die, wherein the first die and the second die are coupled in a stack arrangement(Madan, [p. 262, Introduction, para. 4 -- The proposed processor employs three dies stacked upon each other (see Figure 1); The third die is composed of DRAM banks that serve to augment the L2 cache space provided by the second SRAM die]);
and a cache controller configured to implement a plurality of cache ways of a set associative cache(Madan, [p. 264, section 3.1, para. 1 -- Based on estimates from CACTI 6.0 [32], a 1 MB SRAM cache bank and its associated router/controller have an area roughly equal to the area of one core], [p. 265, 3.2, para. 1 -- If the entire L2 cache size is 16 MB (each bank is 1 MB) and is 4-way set-associative with 64 byte line size, a 64-bit physical address has the following components]) by updating the plurality of cache ways to include a number of cache ways that is based on a number of die of the system which have physical memory and a number of cache ways mapped to the first physical memory of the first die(Madan, [p. 266 3.3 para. 1 -- we propose a reconfigurable cache that takes advantage of 3D stacking to seamlessly grow the size of a bank in the vertical dimension. This allows the size of each bank to grow independently with out impacting the capacity or access time of neighboring banks.], [p. 266, 3.3 para. 4 -- (i) increased associativity, (ii) increased number of sets, and (iii) increased block size.], [p. 271, 4.5 para. 5 – Dynamic reconfiguration ensures that DRAM banks are looked up only when bank pressure is high (typically only in central banks).]), and the plurality of cache ways including a first respective cache way mapped to the first physical memory of the first die(Madan, [p. 263, 1, para. 4 -- where a given physical address maps to a unique bank in the cache (the physical address maps to a unique bank and set within that bank; the ways of the set may be distributed over multiple subarrays within that bank)], [p. 271, sec. 4.5, para. 5 -- Figures 8(a) and 8(b) show the average distribution of
hits in SRAM and DRAM ways for all the cache banks
for Rp:I+Share4:D schemes]) and a second respective cache way mapped to the second physical memory of the second die(Madan, [p. 266, 3.3, para. 2 -- In this case, we advocate the use of a third die that implements DRAM banks, thus allowing the bank size to grow by up to a factor of nine. By stacking a single DRAM die (instead of eight SRAM dies)], [p. 266, 3.3, para. 3 -- As with most large L2s, the tags are first looked up and after the appropriate way is identified, the data subarray is accessed.], [p. 271, sec. 4.5, para. 5 -- Figures 8(a) and 8(b) show the average distribution of
hits in SRAM and DRAM ways for all the cache banks
for Rp:I+Share4:D schemes]).
As per claim 1, Madan discloses:
A system(Madan,p. 265, Fig. 1) comprising:
a first physical memory of a first die(Madan, [p. 262, Introduction, para. 4 -- The second die is composed entirely of SRAM cache banks (forming a large shared L2 cache) and employs an on-chip network so that requests from the CPU can be routed to the correct bank]);
a second physical memory of a second die, wherein the first die and the second die are coupled in a stack arrangement(Madan, [p. 262, Introduction, para. 4 -- The proposed processor employs three dies stacked upon each other (see Figure 1); The third die is composed of DRAM banks that serve to augment the L2 cache space provided by the second SRAM die]);
and a cache controller configured to implement a plurality of cache ways of a set associative cache(Madan, [p. 264, section 3.1, para. 1 -- Based on estimates from CACTI 6.0 [32], a 1 MB SRAM cache bank and its associated router/controller have an area roughly equal to the area of one core], [p. 265, 3.2, para. 1 -- If the entire L2 cache size is 16 MB (each bank is 1 MB) and is 4-way set-associative with 64 byte line size, a 64-bit physical address has the following components]), the plurality of cache ways including a first respective cache way mapped to the first physical memory of the first die(Madan, [p. 263, 1, para. 4 -- where a given physical address maps to a unique bank in the cache (the physical address maps to a unique bank and set within that bank; the ways of the set may be distributed over multiple subarrays within that bank)], [p. 271, sec. 4.5, para. 5 -- Figures 8(a) and 8(b) show the average distribution of
hits in SRAM and DRAM ways for all the cache banks
for Rp:I+Share4:D schemes]) and a second respective cache way mapped to the second physical memory of the second die(Madan, [p. 266, 3.3, para. 2 -- In this case, we advocate the use of a third die that implements DRAM banks, thus allowing the bank size to grow by up to a factor of nine. By stacking a single DRAM die (instead of eight SRAM dies)], [p. 266, 3.3, para. 3 -- As with most large L2s, the tags are first looked up and after the appropriate way is identified, the data subarray is accessed.], [p. 271, sec. 4.5, para. 5 -- Figures 8(a) and 8(b) show the average distribution of
hits in SRAM and DRAM ways for all the cache banks
for Rp:I+Share4:D schemes]]).
As per claim 11, Madan discloses:
A device(Madan,p. 265, Fig. 1) comprising:
a first physical memory integrated within a first die(Madan, [p. 262, Introduction, para. 4 -- The lowest die contains the processing cores (along with the corresponding L1 caches).; The second die is composed entirely of SRAM cache banks (forming a large shared L2 cache) and employs an on-chip network so that requests from the CPU can be routed to the correct bank. ]);
and a cache controller, the cache controller(Madan, [p. 264, sec. 3.1, para. 1 -- Each bank may itself be partitioned into multiple subarrays (as estimated by CACTI 6.0) to reduce latency and power. Each bank is associated with a small cache controller unit and a routing unit. On an L1 miss, the core sends the request to the cache controller unit directly above through an inter-die via pillar]) configured to:
map a plurality of cache ways of a set associative cache,(Madan, [p. 263, sec. 1, para. 5 -- (the physical address maps to a unique bank and set within that bank; the ways of the set may be distributed over multiple subarrays within that bank)], [p. 267, sec. 3.3, para. 1 -- The first form of reconfiguration allows the bank to go from 4-way to 34-way set associative]), the plurality of cache ways including a first cache way defined within the first physical memory(Madan, [p. 263, sec. 1, para. 4 -- where a given physical address maps to a unique bank in the cache (the physical address maps to a unique bank and set within that bank; the ways of the set may be distributed over multiple subarrays within that bank)], [p. 266, sec. 3.3, para. 3 -- As with most large L2s, the tags are first looked up and after the appropriate way is identified, the data subarray is accessed], [p. 267 sec. 3.3 para. 5 -- tag subarrays], )], [p. 271, sec. 4.5, para. 5 -- Figures 8(a) and 8(b) show the average distribution of hits in SRAM and DRAM ways for all the cache banks for Rp:I+Share4:D schemes]);
detect that a second die is coupled to the first die in a stack arrangement(Madan, [p. 262, sec. 1, para. 4 -- The proposed processor employs three dies stacked upon each other (see Figure 1); The third die is composed of DRAM banks that serve to augment the L2 cache space provided by the second SRAM die], [p. 265, sec. 3.2, para. 2 -- This may cause the central banks to enable their additional DRAM cache space.], [p. 269, sec. 4.5 para. 1 -- If an SRAM bank encounters high bank pressure, it enables the DRAM bank directly above.]), the second die including a second physical memory integrated within the second die(Madan, [p. 262 col. Sec. 1, para. 4 -- The third die is composed of DRAM banks that serve to augment the L2 cache space provided by the second SRAM die.], [Fig. 1 – Stacked 3D processor layout]);
and update the plurality of cache ways to include a number of cache ways that is based on a number of die in the stack arrangement which have physical memory and a number of cache ways mapped to the first die, the plurality of cache ways updated to include a second cache way defined within the second physical memory(Madan, [p. 266 sec. 3.3, para. 1 -- Instead, we propose a reconfigurable cache that takes advantage of 3D stacking to seamlessly grow the size of a bank in the vertical dimension], [p. 266 sec. 3.3, para. 2 -- In this case, we advocate the use of a third die that implements DRAM banks, thus allowing the bank size to grow by up to a factor of nine], [p. 267, sec. 3.3, para. 5 -- The first form of reconfiguration allows the bank to go from 4-way to 34-way set associative. 32 data ways are implemented on the DRAM die and two of the original four data ways remain on the SRAM die after half the data subarrays are converted to tag subarrays.], [p. 266, para. 3 -- As with most large L2s, the tags are first looked up and after the appropriate way is identified, the data subarray is accessed.], [p. 267, sec. 3.3, para. 6 -- The second form of reconfiguration causes an increase in the number of sets from 2K to 16K (we will restrict ourselves to power-of-two number of sets, possibly leading to extra white space on the top die).], [p. 266 3.3 para. 1 -- we propose a reconfigurable cache that takes advantage of 3D stacking to seamlessly grow the size of a bank in the vertical dimension. This allows the size of each bank to grow independently with out impacting the capacity or access time of neighboring banks.], [p. 266, 3.3 para. 4 -- (i) increased associativity, (ii) increased number of sets, and (iii) increased block size.], [p. 271, 4.5 para. 5 – Dynamic reconfiguration ensures that DRAM banks are looked up only when bank pressure is high (typically only in central banks).]).
As per claim 12, the rejection of claim 11 is incorporated, in addition, Madan discloses:
wherein the cache controller(Madan, [p. 264, sec. 3.1, para. 1 -- Each bank is associated with a small cache controller unit and a routing unit.]) is configured to update the plurality of cache ways in response to the detection of the second die(Madan, [p. 262, sec. 1, para. 4 -- The third die is composed of DRAM banks that serve to augment the L2 cache space provided by the second SRAM die], [p. 263, sec. 1, para. 6 -- Hence, we instead spill additional pages into the third dimension – to the DRAM bank directly above the SRAM cache bank. Note that the DRAM bank and SRAM bank form a single large vertical slice in the same L2.], [p. 266, para. 3 -- As with most large L2s, the tags are first looked up and after the appropriate way is identified, the data subarray is accessed.], [p. 269, sec. 4.5 para. 1 -- If an SRAM bank encounters high bank pressure, it enables the DRAM bank directly above.]).
As per claim 17, Madan discloses:
A method implemented by a computing device(Madan,p. 265, Fig. 1), the method comprising:
mapping a plurality of cache ways of a set associative cache(Madan, [p. 263, sec. 1, para. 5 -- (the physical address maps to a unique bank and set within that bank; the ways of the set may be distributed over multiple subarrays within that bank)], [p. 267, sec. 3.3, para. 1 -- The first form of reconfiguration allows the bank to go from 4-way to 34-way set associative]), the plurality of cache ways including a first respective cache way defined to be within mapped to a first physical memory(Madan, [p. 263, sec. 1, para. 4 -- where a given physical address maps to a unique bank in the cache (the physical address maps to a unique bank and set within that bank; the ways of the set may be distributed over multiple subarrays within that bank)], [p. 266, sec. 3.3, para. 3 -- As with most large L2s, the tags are first looked up and after the appropriate way is identified, the data subarray is accessed], [p. 267 sec. 3.3 para. 5 -- tag subarrays], [p. 271, sec. 4.5, para. 5 -- Figures 8(a) and 8(b) show the average distribution of hits in SRAM and DRAM ways for all the cache banks for Rp:I+Share4:D schemes]), the first physical memory being integrated within of a first die(Madan, [p. 262, sec. 1, para. 4 -- The lowest die contains the processing cores (along with the corresponding L1 caches).; The second die is composed entirely of SRAM cache banks (forming a large shared L2 cache) and employs an on-chip network so that requests from the CPU can be routed to the correct bank.]);
detecting that a second die is coupled to the first die in a stack arrangement(Madan, [p. 262, sec. 1, para. 4 -- The proposed processor employs three dies stacked upon each other (see Figure 1); The third die is composed of DRAM banks that serve to augment the L2 cache space provided by the second SRAM die], [p. 265, sec. 3.2, para. 2 -- This may cause the central banks to enable their additional DRAM cache space.], [p. 269, sec. 4.5 para. 1 -- If an SRAM bank encounters high bank pressure, it enables the DRAM bank directly above.]) and that a second physical memory is integrated within of the second die(Madan, [p. 262 col. Sec. 1, para. 4 -- The third die is composed of DRAM banks that serve to augment the L2 cache space provided by the second SRAM die.], [Fig. 1 – Stacked 3D processor layout]);
And update the plurality of cache ways to include a number of cache ways that is based on a number of die in the stack arrangement which have physical memory and a number of cache ways mapped to the first die, the plurality of cache ways updated to include a second cache way defined within the second physical memory(Madan, [p. 266 sec. 3.3, para. 1 -- Instead, we propose a reconfigurable cache that takes advantage of 3D stacking to seamlessly grow the size of a bank in the vertical dimension], [p. 266 sec. 3.3, para. 2 -- In this case, we advocate the use of a third die that implements DRAM banks, thus allowing the bank size to grow by up to a factor of nine], [p. 267, sec. 3.3, para. 5 -- The first form of reconfiguration allows the bank to go from 4-way to 34-way set associative. 32 data ways are implemented on the DRAM die and two of the original four data ways remain on the SRAM die after half the data subarrays are converted to tag subarrays.], [p. 266, para. 3 -- As with most large L2s, the tags are first looked up and after the appropriate way is identified, the data subarray is accessed.], [p. 267, sec. 3.3, para. 6 -- The second form of reconfiguration causes an increase in the number of sets from 2K to 16K (we will restrict ourselves to power-of-two number of sets, possibly leading to extra white space on the top die).], [p. 266 3.3 para. 1 -- we propose a reconfigurable cache that takes advantage of 3D stacking to seamlessly grow the size of a bank in the vertical dimension. This allows the size of each bank to grow independently with out impacting the capacity or access time of neighboring banks.], [p. 266, 3.3 para. 4 -- (i) increased associativity, (ii) increased number of sets, and (iii) increased block size.], [p. 271, 4.5 para. 5 – Dynamic reconfiguration ensures that DRAM banks are looked up only when bank pressure is high (typically only in central banks).]).
As per claim 18, the rejection of claim 17 is incorporated, in addition, Madan discloses:
wherein updating the plurality of cache ways is in response to the detection of the second die(Madan, [p. 262, sec. 1, para. 4 -- The third die is composed of DRAM banks that serve to augment the L2 cache space provided by the second SRAM die], [p. 263, sec. 1, para. 6 -- Hence, we instead spill additional pages into the third dimension – to the DRAM bank directly above the SRAM cache bank. Note that the DRAM bank and SRAM bank form a single large vertical slice in the same L2.], [p. 266, para. 3 -- As with most large L2s, the tags are first looked up and after the appropriate way is identified, the data subarray is accessed.], [p. 269, sec. 4.5 para. 1 -- If an SRAM bank encounters high bank pressure, it enables the DRAM bank directly above.]).
As per claim 21, the rejection of claim 1 is incorporated, in addition, Madan discloses:
wherein the first respective cache way is mapped to the first physical memory of the first die only and the second respective cache way is mapped to the second physical memory of the second die only(Madan, [p. 266, 3.3 para. 1 -- This allows the size of each bank to grow independently with out impacting the capacity or access time of neighboring banks.]).
As per claim 22, the rejection of claim 1 is incorporated, in addition, Madan discloses:
wherein the number of cache ways is a multiple of the number of die of the system which have physical memory and the number of cache ways mapped to the first physical memory of the first die(Madan, [p. 266, 3.3 para. 2 -- thus allowing the bank size to grow by a factor of two.; In this case, we advocate the use of a third die that implements DRAM banks, thus allowing the bank size to grow by up to a factor of nine]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madan et al.(“Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy”, 2008), and further in view of Mathuriya et al.(20240402908).
As per claim 2, the rejection of claim 1 is incorporated, in addition, Madan does not explicitly disclose the following in its entirety, however Mathuriya discloses:
wherein the cache controller is further configured to select one of the plurality of cache ways to cache data in the set associative cache or to evict the cached data from the set associative cache(Mathuriya, [0170 -- When data region 2805 is used to implement a cache, tags may be used to identify which addresses map to which physical locations in the bank. The cache may be set associative in which a particular address can map to several physical locations. The specific physical location a newly allocated address is mapped to may be determined by a replacement algorithm such as LRU (least recently used) or pseudo-LRU, or even random]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Mathuriya into the system of Madan for the benefit of improving performance of an artificial intelligence (AI) processing system resulting in an ultra-high bandwidth AI processing system, yield of the dies and inter-core access by the compute dies to each coherent cache or memory-side buffer chiplet, performing a high capacity memory process for the die to allow reduction of power of external interconnects to the memory, and reducing cost of integration, latency of computing a training model and using the training model, power consumption of the AI processor systems and perforation requirement for a bottom die(Mathuriya, [0002]).
Claim 13 is a device claim that contains similar limitations to claim 2, and therefore the same mappings are incorporated.
Claim(s) 3, 4, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madan et al.(“Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy”, 2008), in view of Mathuriya et al.(20240402908), and further in view of Loh et al.(20120311269).
As per claim 3, the rejection of claim 2 is incorporated, in addition, Madan does not explicitly disclose the following in its entirety, however Loh discloses:
wherein the cache controller is configured to select the one of the plurality of cache ways based at least in part on die characteristics of the first die and the second die(Loh, [0032 -- According to various embodiments, caching logic may be configured to implement cache management policies that consider the relative performance penalties of evicting different cache blocks. Such a performance penalty may take the form of any performance characteristic of the memory from which a given block is cached. ]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Loh into the system of Madan for the benefit of performing a writeback to a processor's local memory can be significantly faster than performing a writeback to remote memory attached to a different processor, so that a policy that attempts to minimize number of eviction penalties without regard to respective magnitudes can be sub-optimal. The apparatus is designed such that evicting blocks that are not dirty instead of dirty blocks can minimize external buffer usage and increase opportunities for writes to the cache block to be coalesced with the cache even if the writeback operation does not block a pending insertion(Loh, [0076]).
As per claim 4, the rejection of claim 3 is incorporated, in addition, Madan does not explicitly disclose the following in its entirety, however Loh discloses:
wherein the die characteristics include at least one of latency, data communication bandwidth, or memory space availability(Loh, [0031 -- Accordingly, the term "performance characteristic," as used herein, refers to any metric of performing an access to a given system memory, such as a latency, bandwidth, power consumption, reliability, write-endurance, or any other characteristic of the memory.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Loh into the system of Madan for the benefit of performing a writeback to a processor's local memory can be significantly faster than performing a writeback to remote memory attached to a different processor, so that a policy that attempts to minimize number of eviction penalties without regard to respective magnitudes can be sub-optimal. The apparatus is designed such that evicting blocks that are not dirty instead of dirty blocks can minimize external buffer usage and increase opportunities for writes to the cache block to be coalesced with the cache even if the writeback operation does not block a pending insertion(Loh, [0076]).
Claim 14 is a device claim that contains similar limitations to claim 3, and therefore the same mappings are incorporated.
Claim(s) 5, 6, 7, 8, 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madan et al.(“Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy”, 2008), in view of Mathuriya et al.(20240402908), and further in view of Roberts et al.(20220058132).
As per claim 5, the rejection of claim 2 is incorporated, in addition, Madan does not explicitly disclose the following in its entirety, however Roberts discloses:
wherein the cache controller is configured to select the one of the plurality of cache ways based at least in part on data characteristics of the cached data(Roberts, [0066 -- Similarly, reducing the size of the second portion 126 allocated for the second portion 126 may include evicting cache data 128 from one or more cache units 220. The cache data 128 may be evicted according to a policy (a replacement or eviction policy), which may include, but is not limited to: First In First Out (FIFO), Last In First Out (LIFO), Least Recently Used (LRU), Time Aware LRU (TLRU), Most Recently Used (MRU), Least-Frequently Used (LFU), random replacement, and/or the like.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Roberts into the system of Madan for the benefit of utilizing the cache memory to enable quick responses from the memory system based on desired data present in the cache, thus increasing probability that desired data is present in the cache. The method enables allowing a prefetching system to utilize the cache memory to accelerate memory access operations, thus reducing operational complexity(Roberts, [0025]).
As per claim 6, the rejection of claim 5 is incorporated, in addition, Madan does not explicitly disclose the following in its entirety, however Roberts discloses:
wherein the data characteristics include at least one of data access frequency or quality of service metrics associated with the cached data(Roberts, [0066 -- Similarly, reducing the size of the second portion 126 allocated for the second portion 126 may include evicting cache data 128 from one or more cache units 220. The cache data 128 may be evicted according to a policy (a replacement or eviction policy), which may include, but is not limited to: First In First Out (FIFO), Last In First Out (LIFO), Least Recently Used (LRU), Time Aware LRU (TLRU), Most Recently Used (MRU), Least-Frequently Used (LFU), random replacement, and/or the like.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Roberts into the system of Madan for the benefit of utilizing the cache memory to enable quick responses from the memory system based on desired data present in the cache, thus increasing probability that desired data is present in the cache. The method enables allowing a prefetching system to utilize the cache memory to accelerate memory access operations, thus reducing operational complexity(Roberts, [0025]).
As per claim 7, the rejection of claim 2 is incorporated, in addition, Madan does not explicitly disclose the following in its entirety, however Roberts discloses:
wherein the cache controller is configured to select the one of the plurality of cache ways based at least in part on a state of a system component associated with the data(Roberts, [0022 -- In some implementations, prefetching performance can be improved by maintaining metadata pertaining to respective regions of the address space. The metadata utilized by the prefetcher may include a plurality of entries, with each entry including information pertaining to memory accesses with a respective region of the address space. The prefetcher may utilize metadata pertaining to respective regions to inform prefetch operations within the respective regions.).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Roberts into the system of Madan for the benefit of utilizing the cache memory to enable quick responses from the memory system based on desired data present in the cache, thus increasing probability that desired data is present in the cache. The method enables allowing a prefetching system to utilize the cache memory to accelerate memory access operations, thus reducing operational complexity(Roberts, [0025]).
As per claim 8, the rejection of claim 7 is incorporated, in addition, Madan does not explicitly disclose the following in its entirety, however Roberts discloses:
wherein the state of the system component includes at least one of the system component requesting the data as part of a pre-fetch command, or the system component requesting the data for execution(Roberts, [0022 -- In some implementations, prefetching performance can be improved by maintaining metadata pertaining to respective regions of the address space. The metadata utilized by the prefetcher may include a plurality of entries, with each entry including information pertaining to memory accesses with a respective region of the address space. The prefetcher may utilize metadata pertaining to respective regions to inform prefetch operations within the respective regions.], [0092 -- The cache logic 210 (and/or partition logic 310) may be configured to preserve cache state when repartitioning the cache memory 120 to increase the size of the first portion 124 and/or decrease the size of the second portion 126. The cache logic 210 may preserve cache state when reducing the amount of cache memory 120 allocated to the second portion 126 by, inter alia, compacting cache data 128 stored within the second portion 126 for storage within fewer cache units 220.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Roberts into the system of Madan for the benefit of utilizing the cache memory to enable quick responses from the memory system based on desired data present in the cache, thus increasing probability that desired data is present in the cache. The method enables allowing a prefetching system to utilize the cache memory to accelerate memory access operations, thus reducing operational complexity(Roberts, [0025]).
Claim 15 is a device claim that contains similar limitations to claim 5, and therefore the same mappings are incorporated.
Claim 16 is a device claim that contains similar limitations to claim 7, and therefore the same mappings are incorporated.
Claim(s) 9, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madan et al.(“Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy”, 2008), in view of Mathuriya et al.(20240402908), and further in view of Seo et al.(20240248848).
As per claim 9, the rejection of claim 2 is incorporated, in addition, Madan does not explicitly disclose the following in its entirety, however Seo discloses:
wherein the cache controller is further configured to select the one of the plurality of cache ways based at least in part on a power consumption of the system or a system component(Seo, [0070 -- When power consumption of the system 400 increases as the number of ways to which power is supplied in the selected way group increases (Yes), the controller 430 may determine not to further increase the number of ways to which power is supplied (S1210).]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Seo into the system of Madan for the benefit of increasing the number of ways to which power is supplied in the selected one way group, so that power efficiency of the set-associative cache is improved, thus reducing power consumption of the system(Seo, [0056]).
As per claim 10, the rejection of claim 9 is incorporated, in addition, Madan does not explicitly disclose the following in its entirety, however Seo discloses:
wherein the cache controller is further configured to, in response to the power consumption exceeding a threshold level: transfer cached data out of the second physical memory; update the set associative cache to remove the second cache way from the plurality of cache ways; and reduce an amount of power provided to the second die(Seo, [0087 -- When the throughput of the IP block is higher than a second threshold (Case 3), the controller 430 may select both the first and second way groups (S1630), and when the throughput of the IP block is higher than a first threshold (Case 2), the controller 430 may select the second way group (S1620), and in other cases (Case 1), the controller 430 may select the first way group (S1610). The second threshold may be greater than the first threshold, and the first and second thresholds may be previously determined.]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the features of Seo into the system of Madan for the benefit of increasing the number of ways to which power is supplied in the selected one way group, so that power efficiency of the set-associative cache is improved, thus reducing power consumption of the system(Seo, [0056]).
Response to Arguments
Applicant's arguments filed 02/06/2026 have been fully considered but they are not persuasive.
Applicant contends that the following limitation distinguishes the claims from the prior art:
…updating the plurality of cache ways to include a number of cache ways that is based on a number of die of the system which have physical memory and a number of cache ways mapped to the first physical memory of the first die, and the plurality of cache ways including a first respective cache way mapped to the first physical memory of the first die and a second respective cache way mapped to the second physical memory of the second die…
The USPTO disagrees with this contention. The prior art of Madan describes a heterogeneous reconfigurable cache design that takes advantage of the high density of DRAM and the superior power/delay characteristics of SRAM to efficiently meet the working set demands of each individual core. As each die is stacked, the overall capacity of the layout increases, but allowing for a smaller footprint because of the vertical stacking and reducing latency due to the page coloring methods. The reasoning for Madan disclosing this limitation is elaborated above. All rejections are maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARVIND TALUKDAR whose telephone number is (303)297-4475. The examiner can normally be reached M-F, 10 am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132