DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 1 requires “selectively transmitting the first reference voltage to a node according to the bias voltage.” What about the bias voltage determines the selection of transmission? Does the bias voltage need to be high? Does the bias voltage need to be low? Does the bias voltage need to have a particular frequency? Does the bias voltage need to have a particular offset from the reference voltage? When is the reference voltage selectively transmitted? Is it transmitted in response to a bias voltage that interferes with the reference voltage? There is a similar requirement in independent claim 6 and it is rejected in the same manner as claim 1. Claim 2 also contains similar language requiring “a switch, selectively turned on according to the bias voltage to transmit the first reference voltage to the node.” Claim 7 also contains similar language requiring “selectively turning on a switch according to the bias voltage to transmit the first reference voltage to the node.” Claims 2 & 7contain the same or similar language are similarly rejected for the same reasons discussed above. All subsequent claims that depend from both claims 1, 2, 6, & 7 are also rejected.
Independent claim 1 requires “outputting a second reference voltage via the node, and holding a level of the second reference voltage after stopping transmitting the first reference voltage to the node.” When and why was the first reference voltage stopped from being transmitted to the node? What stops the transmission? What initiates the stopping of the transmission? There is a similar requirement in independent claim 6 and it is rejected in the same manner as claim 1. All subsequent claims that depend from both claims 1 & 6 are also rejected.
Claim 4 requires “the level hold circuit holds a level of the second reference voltage for a period of time.” What is the period of time? What defines the period? Is it a second? Is it a minute? Is it a day? Is it a weak? Is it a year? Clarification is required.
Claim 5 requires “generating an enable signal according to a clock signal at power-on of the power supply voltage, wherein the comparator circuit is further activated according to the enable signal to start comparing the second reference voltage with the detection voltage.” What is it in the clock-signal that determines the generation of the enable signal? Is there a pattern in the clock-signal that necessitates the generation of the enable signal? If there is, what is the necessary pattern? Is it a frequency? Is it a delay time? Clarification is required. Claims 9 & 10 require a similar limitation and are similarly rejected.
The claims will be interpreted using the broadest reasonable interpretation in light of the 112 2nd rejection above to advance prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 6, & 8 are rejected under 35 U.S.C. 102(a)(1) & (a)(2) as being anticipated by Kamimurai et al (U.S. PGPub # 2017/0279390).
Regarding Independent claim 1, Kamimurai teaches:
A power detector device, comprising:
a voltage generator circuit (Fig. 1 Element Battery & Fig. 2 Element Phase Voltage Input.), generating a bias voltage (Fig. 2 Element Phase Voltage Input. See Abstract & paragraphs 0007-0009, 0011, 0032, 0042, & 0044 wherein there is disclosed a DC bias voltage of the phase voltage signal.) and a detection voltage according to a power supply voltage (Fig. 2 Element Phase Voltage Input. See Abstract & paragraphs 0007-0009, 0011, 0032, 0042, & 0044 wherein there is disclosed a DC bias voltage of the phase voltage signal. The phase voltage signal is the detection signal.);
a reference circuit, generating a first reference voltage according to the power supply voltage (Fig. 1 Element Battery & Fig. 2 Element Reference Potential.);
a level hold circuit (Fig. 2 Element 110.), selectively transmitting the first reference voltage to a node according to the bias voltage (Fig. 2 Node B and input of op-amp 111.), outputting a second reference voltage via the node (Fig. 2 Elements 110 and output of 111.), and holding a level of the second reference voltage after stopping transmitting the first reference voltage to the node (Fig. 2 Element 120 and node C.); and
a comparator circuit (Fig. 2 Element 130.), comparing the second reference voltage with the detection voltage to generate a power detection signal (Fig. 2 Element 130.).
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Regarding claim 3, Kamimurai teaches all elements of claim 1, upon which this claim depends.
Kamimurai teaches the voltage generator circuit divides the power supply voltage to generate the bias voltage and the detection voltage (Fig. 2 Element Phase Voltage Input wherein the voltage splits at Node A.).
Regarding claim 6, Kamimurai teaches:
A power detection method, comprising:
generating a bias voltage (Fig. 2 Element Phase Voltage Input. See Abstract & paragraphs 0007-0009, 0011, 0032, 0042, & 0044 wherein there is disclosed a DC bias voltage of the phase voltage signal.) and a detection voltage according to a power supply voltage (Fig. 2 Element Phase Voltage Input. See Abstract & paragraphs 0007-0009, 0011, 0032, 0042, & 0044 wherein there is disclosed a DC bias voltage of the phase voltage signal. The phase voltage signal is the detection signal.);
generating a first reference voltage according to the power supply voltage (Fig. 1 Element Battery & Fig. 2 Element Reference Potential.);
selectively transmitting the first reference voltage to a node according to the bias voltage (Fig. 2 Node B and input of op-amp 111.), outputting a second reference voltage via the node (Fig. 2 Elements 110 and output of 111.), and holding a level of the second reference voltage after the transmitting of the first reference voltage to the node is stopped (Fig. 2 Element 120 and node C.); and
comparing the second reference voltage with the detection voltage to generate a power detection signal (Fig. 2 Element 130.).
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Regarding claim 8, Kamimurai teaches all elements of claim 1, upon which this claim depends.
Kamimurai teaches the generating of the bias voltage and the detection voltage according to the power supply voltage comprises: dividing the power supply voltage to generate the bias voltage and the detection voltage Fig. 2 Element Phase Voltage Input wherein the voltage splits at Node A.).
Allowable Subject Matter
Claims 2, 4-5, 7, & 9-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art listed does not anticipate alone or combine in an obvious manner to teach the invention claimed by applicant.
Regarding claim 2, Kamimurai teaches all elements of claim 1, upon which this claim depends.
Kamimurai does not explicitly teach the level hold circuit comprises: a switch, selectively turned on according to the bias voltage to transmit the first reference voltage to the node; and a capacitor, coupled between the node and ground, charged by the first reference voltage to generate the second reference voltage.
Regarding claim 4, Kamimurai teaches all elements of claim 1, upon which this claim depends.
Kamimurai does not explicitly teach when a level of the power supply voltage starts to decrease, a level of the bias voltage and a level of the detection voltage start to lower, and the level hold circuit holds a level of the second reference voltage for a period of time.
Regarding claim 5,
The power detector device according to claim 1, further comprising: a delay circuit, generating an enable signal according to a clock signal at power-on of the power supply voltage, wherein the comparator circuit is further activated according to the enable signal to start comparing the second reference voltage with the detection voltage.
Regarding claim 7,
The power detection method according to claim 6, wherein the selectively transmitting of the first reference voltage to the node according to the bias voltage, the outputting of the second reference voltage via the node, and the holding of the level of the second reference voltage after the transmitting of the first reference voltage to the node is stopped comprise: selectively turning on a switch according to the bias voltage to transmit the first reference voltage to the node; and charging a capacitor by the first reference voltage to generate the second reference voltage, wherein the capacitor is coupled between the node and ground.
Regarding claim 9,
The power detection method according to claim 6, wherein the selectively transmitting of the first reference voltage to the node according to the bias voltage, the outputting of the second reference voltage via the node, and the holding of the level of the second reference voltage after the transmitting of the first reference voltage to the node is stopped comprise: holding the level of the second reference voltage for a period of time when the level of the power supply voltage starts to decrease, wherein a level of the bias voltage and a level of the detection voltage start to lower when the level of the power supply voltage starts to decrease.
Regarding claim 10,
The power detection method according to claim 6, wherein the comparing of the second reference voltage with the detection voltage to generate the power detection signal comprises: starting comparing the second reference voltage with the detection voltage according to an enable signal, wherein the enable signal is generated by a delay circuit according to a clock signal at power-on of the power supply voltage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art listed but not cited represents the previous state of the art and analogous art that teaches some of the limitations claimed by applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER P MCANDREW whose telephone number is (469)295-9025. The examiner can normally be reached Monday-Thursday 6-4:30.
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/CHRISTOPHER P MCANDREW/Primary Examiner, Art Unit 2858