Prosecution Insights
Last updated: August 16, 2026
Application No. 18/621,706

DOHERTY AMPLIFIER CIRCUIT

Non-Final OA §102
Filed
Mar 29, 2024
Priority
Mar 31, 2023 — JP 2023-058638 +1 more
Examiner
NGUYEN, HIEU P
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1139 granted / 1237 resolved
+32.1% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
20 currently pending
Career history
1252
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
55.7%
+15.7% vs TC avg
§102
28.2%
-11.8% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1237 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement filed on 03/29/2024 has been considered and placed in the application file. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 and 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maxim et al. (U.S. 2023/0387861). Regarding claim 1, Maxim et al. (hereinafter, Ref~861) discloses (please see Fig. 3 and related text for details) a Doherty amplifier circuit (10 of Fig. 3) comprising: a first integrated circuit (CMOS Die of Fig. 3); and a second integrated circuit (GaAs Die of Fig. 3) connected to the first integrated circuit, wherein the first integrated circuit comprises: a carrier amplifier (22 of Fig. 3) configured to amplify a radio-frequency signal (RFIN of Fig. 3), a peak amplifier (26 of Fig. 3) configured to amplify the radio-frequency signal, and a variable gain control circuit (e.g., 64 and/or 68 of Fig. 3 at least) configured to control a gain of the radio-frequency signal based on a drive level signal (control signal from 36 of Fig. 3) that indicates a drive level (Sat Det of Fig. 3) of the carrier amplifier, wherein a state of operation of the peak amplifier is controlled based on an output from the variable gain control circuit as described throughout the disclosure (see paragraph [0029-0047]), and wherein the first integrated circuit is on a silicon die (a typical CMOS die would be made from Silicon), meeting claim 1. Regarding claim 2, Ref~861 discloses the Doherty amplifier circuit according to Claim 1, further comprising: a bias circuit (65 of Fig. 3) configured to input a bias to the peak amplifier based on the output from the variable gain control circuit from the teaching that “the bias and the variable gain of the peaking driver input driver input stage 26 is controlled by the activation signal generated by the saturation detector 34” as described in paragraph [0061], meeting claim 2. Regarding claim 4, Ref~861 discloses the Doherty amplifier circuit according to Claim 1, wherein the carrier amplifier comprises: a driver stage carrier amplifier (22 of Fig. 3), and a power stage carrier amplifier (16 of Fig. 3) configured to accept an output from the driver stage carrier amplifier as an input, wherein the peak amplifier comprises: a driver stage peak amplifier (26 of Fig. 3), and a power stage peak amplifier (18 of Fig. 3) configured to accept an output from the driver stage peak amplifier as an input, and wherein the first integrated circuit on the silicon die further comprises: a distribution circuit (28 of Fig. 3) configured to input the radio-frequency signal to the carrier amplifier and to the peak amplifier as signals having different phases from each other, the driver stage carrier amplifier, and the driver stage peak amplifier, meeting claim 4. Regarding claim 5, Ref~861 discloses the Doherty amplifier circuit according to Claim 2, wherein the carrier amplifier comprises: a driver stage carrier amplifier (22 of Fig. 3), and a power stage carrier amplifier (16 of Fig. 3) configured to accept an output from the driver stage carrier amplifier as an input, wherein the peak amplifier comprises: a driver stage peak amplifier (26 of Fig. 3), and a power stage peak amplifier (18 of Fig. 3) configured to accept an output from the driver stage peak amplifier as an input, and wherein the first integrated circuit on the silicon die further comprises: a distribution circuit (28 of Fig. 3) configured to input the radio-frequency signal (RFIn of Fig. 3) to the carrier amplifier and to the peak amplifier as signals having different phases (90 degrees) from each other, the driver stage carrier amplifier, and the driver stage peak amplifier, meeting claim 5. Allowable Subject Matter Claims 3 and 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YOUNGHUIE HAN (Jessica) can be reached on 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HIEU P NGUYEN/Primary Examiner, Art Unit 2843
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Prosecution Timeline

Mar 29, 2024
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12706570
DIFFERENTIAL DOHERTY AMPLIFIER CIRCUIT
2y 9m to grant Granted Aug 11, 2026
Patent 12702015
SEMICONDUCTOR DEVICE
2y 8m to grant Granted Aug 04, 2026
Patent 12700833
POWER AMPLIFIER
2y 7m to grant Granted Aug 04, 2026
Patent 12695429
AMPLIFIER WITH CASCODE ARRANGEMENT
3y 3m to grant Granted Jul 28, 2026
Patent 12695516
RECEIVER CIRCUIT AND OPTICAL RECEIVER CIRCUIT
2y 7m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.2%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1237 resolved cases by this examiner. Grant probability derived from career allowance rate.

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