Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the second tile" in line 9. There is insufficient antecedent basis for this limitation in the claim. It is unclear to which second tile this refers.
Claim 8 recites the limitation "the second tile" in lines 6-7. There is insufficient antecedent basis for this limitation in the claim. It is unclear to which second tile this refers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis et al. (U.S. PGPUB 20150062154) in view of Bhiravabhatla et al. (U.S. PGPUB 20240104684).
With respect to claim 1, Ellis et al. disclose an acceleration unit (AU) (paragraph 197, graphics processor and to a graphics processing platform including the apparatus of or operated in accordance with any one or more of the embodiments of the technology described herein. Subject to any hardware necessary to carry out the specific functions discussed above, such a graphics processor can otherwise include any one or more or all of the usual functional units, etc., that graphics processors include) comprising: one or more caches (paragraph 263, As shown in FIG. 10, the tile shader 14 can also operate to store data in and read data from the main memory 16 and cache memory 15. This then allows the tile shader 14 to store sampling position values from a tile for use with an adjacent tile and to make use of adjacent tile data values stored in the main memory 16 and cache 15 when performing its processing operations); and one or more processor cores (paragraph 210, Each of the tiles 102 will be processed individually by a graphics processing core) coupled to the one or more caches (paragraph 244, each of the stages, elements and units, etc., of the graphics processing pipeline as shown in FIG. 10 may be implemented as desired and will accordingly comprise, e.g., appropriate circuitry and/or processing logic, etc., for performing the necessary operation and functions) and configured to:
partition a frame to be rendered into a plurality of tiles (paragraph 235, In step 802, as discussed above, initial rendering is performed in respect of each sampling position 104 of the particular tile 102 in order to derive sampling position values (depth, colours and transparency) for each of the sampling positions 104, Fig. 7, frame is partitioned into tiles 102)
for a first tile of the plurality of tiles, write pixel attribute data of primitives at least partially visible in the first tile to the one or more caches (paragraph 254, (The tile buffer will store, as is known in the art, colour and depth buffers that store an appropriate colour, etc., or Z-value, respectively, for each sampling point that the buffers represent (in essence for each sampling point of a tile that is being processed).), paragraph 256, The tile buffer is provided as part of RAM that is located on (local to) the graphics processing pipeline (chip), paragraph 257, The data from the tile buffer 10 is input to a downsampling (multisample resolve) write out unit 13, and thence output (written back) to an external memory output buffer, such as a frame buffer of a display device (not shown), in main memory 16. There may also be a cache 15, associated with the main memory 16, as is known in the art); and
based on the pixel attribute data of the primitives at least partially visible in the first tile stored in the one or more caches, determine lighting data for the primitives at least partially visible in the first tile (paragraph 288, This processing pass may generate, for example, render targets for the tile comprising colour, depth, surface normals, and other attributes that are then stored separately in the tile buffer 10. (As is known in the art, when performing deferred shading, these values are then used to do complex light calculations and composition to produce the final desired output result.)). However, Ellis et al. do not expressly disclose before determining lighting data for the primitives at least partially visible in the first tile, begin writing pixel attribute data of primitives at least partially visible in the second tile.
Bhiravabhatla et al., who also deal with tiled rendering, disclose a method for before determining lighting data for the primitives at least partially visible in the first tile, begin writing pixel attribute data of primitives at least partially visible in the second tile (paragraph 30, 1) a bin visibility pass (also referred to hereinafter as a binning pass) that includes streaming the geometry positions (e.g., vertices) into the GPU, where triangle level visibility tests may be performed and low resolution Z (LRZ) buffer and the visibility buffer may be primed, and then the triangles may be sorted into various bins with the visibility information recorded, paragraph 61, The results of the visibility check 404 may be the visibility data/LRZ buffer 414. The positions 412 and the visibility data/LRZ buffer 414 may be stored in the memory 450 (e.g., DDR/main memory), paragraph 62, the visibility data/LRZ buffer 416 and the positions/attributes 418, which may be stored in the memory 450, may correspond to the visibility data/LRZ buffer 414 and the positions 412 in the binning pipeline 430… The pixel pipeline 408 may perform per-pixel tests and operations (e.g., depth tests, pixel blending, etc.) and programmable shading and lighting before outputting the final color). Since Bhiravabhatla et al. disclose a bin visibility pass for sorting triangles into various bins, this includes at least a first and second tile. The positions/attributes are stored in memory 450 before shading and lighting before outputting the final color.
Ellis et al. and Bhiravabhatla et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method of before determining lighting data for the primitives at least partially visible in the first tile, begin writing pixel attribute data of primitives at least partially visible in the second tile, as taught by Bhiravabhatla et al., to the Ellis et al. system, because in a rendering pass, the primitives in each bin can be rendered separately. In these instances, the visibility stream can be fetched from memory used to drop primitives which are not visible for that bin (paragraph 53 of Bhiravabhatla et al.), thus improving system performance.
With respect to claim 8, Ellis et al. as modified by Bhiravabhatla et al. disclose a method, as executed by the system of claim 1; see rationale for rejection of claim 1.
Claim(s) 2-3 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis et al. (U.S. PGPUB 20150062154) in view of Bhiravabhatla et al. (U.S. PGPUB 20240104684) and further in view of Hakura et al. (U.S. PGPUB 20180307490).
With respect to claim 2, Ellis et al. as modified by Bhiravabhatla et al. disclose the AU of claim 1. However, Ellis et al. as modified by Bhiravabhatla et al. do not expressly disclose the one or more processor cores are configured to: release the pixel attribute data of primitives at least partially visible in the first tile stored in the one or more caches; and concurrently with releasing pixel attribute data of primitives at least partially visible in the first tile stored in the one or more caches, write the pixel attribute data of the primitives at least partially visible in the second tile of the plurality of tiles to the one or more caches.
Hakura et al., who also deal with tiled rendering, disclose a method wherein the one or more processor cores are configured to: release the pixel attribute data of primitives at least partially visible in the first tile stored in the one or more caches; and concurrently with releasing pixel attribute data of primitives at least partially visible in the first tile stored in the one or more caches, write the pixel attribute data of the primitives at least partially visible in the second tile of the plurality of tiles to the one or more caches (paragraph 63, Once the graphics primitives associated with the first cache tile are processed by the screen space pipeline 354, the portion of the L2 caches associated with the first cache tile may be flushed and the tiling unit may transmit graphics primitives associated with a second cache tile).
Ellis et al., Bhiravabhatla et al., and Hakura et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the one or more processor cores are configured to: release the pixel attribute data of primitives at least partially visible in the first tile stored in the one or more caches; and concurrently with releasing pixel attribute data of primitives at least partially visible in the first tile stored in the one or more caches, write the pixel attribute data of the primitives at least partially visible in the second tile of the plurality of tiles to the one or more caches, as taught by Hakura et al., to the Ellis et al. as modified by Bhiravabhatla et al. system, because the overall memory traffic to the L2 caches and to the render targets may be reduced (paragraph 63 of Hakura et al.).
With respect to claim 3, Ellis et al. as modified by Bhiravabhatla et al. and Hakura et al. disclose the AU of claim 2, wherein the one or more processor cores are configured to: based on the pixel attribute data of the primitives at least partially visible in the second tile stored in the one or more caches, determine lighting data for the primitives at least partially visible in the second tile (Hakura et al.: paragraph 76, Such configurations could include storage for various information, including, without limitation, 3D positional data, diffuse lighting information, and specular lighting information).
With respect to claim 9, Ellis et al. as modified by Bhiravabhatla et al. and Hakura et al. disclose the method of claim 8, as executed by the system of claim 2; see rationale for rejection of claim 2.
With respect to claim 10, Ellis et al. as modified by Bhiravabhatla et al. and Hakura et al. disclose the method of claim 9, as executed by the system of claim 3; see rationale for rejection of claim 3.
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis et al. (U.S. PGPUB 20150062154) in view of Bhiravabhatla et al. (U.S. PGPUB 20240104684) and further in view of Shao et al. (U.S. PGPUB 20230298249).
With respect to claim 4, Ellis et al. as modified by Bhiravabhatla et al. disclose the AU of claim 1. However, Ellis et al. as modified by Bhiravabhatla et al. do not expressly disclose the one or more processor cores are configured to: based on determining the lighting data for the primitives at least partially visible in the first tile, discard the pixel attribute data of the primitives at least partially visible in the first tile.
Shao et al., who also deal with tiled rendering, disclose a method wherein the one or more processor cores are configured to: based on determining the lighting data for the primitives at least partially visible in the first tile, discard the pixel attribute data of the primitives at least partially visible in the first tile (paragraph 94, It would also be possible if desired, to determine whether to retain or discard vertex shaded attributes data generated by the first vertex shading operation on a more dynamic, e.g. primitive-by-primitive basis).
Ellis et al., Bhiravabhatla et al., and Shao et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the one or more processor cores are configured to: based on determining the lighting data for the primitives at least partially visible in the first tile, discard the pixel attribute data of the primitives at least partially visible in the first tile, as taught by Shao et al., to the Ellis et al. as modified by Bhiravabhatla et al. system, because a memory bandwidth saving associated with discarding the vertex shaded position attributes for a primitive may outweigh a potential arithmetic cost associated with processing (shading) position attributes for the primitive a second time during subsequent processing on a per-tile basis (paragraph 91 of Shao et al.).
With respect to claim 11, Ellis et al. as modified by Bhiravabhatla et al. and Shao et al. disclose the method of claim 8, as executed by the system of claim 4; see rationale for rejection of claim 4.
Claim(s) 5-6, 12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis et al. (U.S. PGPUB 20150062154) in view of Bhiravabhatla et al. (U.S. PGPUB 20240104684) and further in view of Lee et al. (U.S. PGPUB 20160117855).
With respect to claim 5, Ellis et al. as modified by Bhiravabhatla et al. disclose the AU of claim 1. However, Ellis et al. as modified by Bhiravabhatla et al. do not expressly disclose the one or more processor cores are configured to perform a visibility pass that determines which primitives of a batch of primitives of the frame are at least partially visible in each tile of the plurality of tiles.
Lee et al., who also deal with tiled rendering, disclose a method wherein the one or more processor cores are configured to perform a visibility pass that determines which primitives of a batch of primitives of the frame are at least partially visible in each tile of the plurality of tiles (paragraph 64, Accordingly, the visibility test unit 120 may detect at least one visible primitive from among a plurality of primitives (for example, the first through third primitives A, B, and C) included in the tile).
Ellis et al., Bhiravabhatla et al., and Lee et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the one or more processor cores are configured to perform a visibility pass that determines which primitives of a batch of primitives of the frame are at least partially visible in each tile of the plurality of tiles, as taught by Lee et al., because this would implement performing visibility examination on a primitive are provided, thereby removing unnecessary calculation and reducing power consumption (paragraph 8 of Lee et al.).
With respect to claim 6, Ellis et al. as modified by Bhiravabhatla et al. and Lee et al. disclose the AU of claim 5, wherein the visibility pass includes writing, for each tile of the plurality of tiles, geometry data of primitives of the batch of primitives at least partially visible in the tile to a queue allocated to the tile (Lee et al.: paragraph 72, The tag buffer 325 stores primitive information about a primitive which the ray intersects with respect to pixels included in the tiles. For example, as shown in FIGS. 4A and 4B, the tag buffer 325 may store the primitive intersection information corresponding to a corresponding pixel).
With respect to claim 12, Ellis et al. as modified by Bhiravabhatla et al. and Lee et al. disclose the method of claim 8, as executed by the system of claim 5; see rationale for rejection of claim 5.
With respect to claim 14, Ellis et al. as modified by Bhiravabhatla et al. and Lee et al. disclose the method of claim 12, as executed by the system of claim 6; see rationale for rejection of claim 6.
Claim(s) 7 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ellis et al. (U.S. PGPUB 20150062154) in view of Bhiravabhatla et al. (U.S. PGPUB 20240104684), Lee et al. (U.S. PGPUB 20160117855), and further in view of Brigg et al. (U.S. PGPUB 20210110510).
With respect to claim 7, Ellis et al. as modified by Bhiravabhatla et al. and Lee et al. disclose the AU of claim 5. However, Ellis et al. as modified by Bhiravabhatla et al. and Lee et al. do not expressly disclose the one or more processor cores are configured to form the batch of primitives to be rendered based on a queue allocated to a corresponding tile of the plurality of tiles reaching a capacity threshold.
Brigg et al., who also deal with tiled rendering, disclose a method wherein the one or more processor cores are configured to form the batch of primitives to be rendered based on a queue allocated to a corresponding tile of the plurality of tiles reaching a capacity threshold (paragraph 92, the top level sorting logic 404 may be configured to, if it determines that a primitive falls within a specific top-level region, determine if there is a queue allocated to that top level region. If there is a queue allocated to/associated with that top level region, then the top level sorting logic 404 may determine whether that queue is full. If the queue is not full the top level sorting logic 404 may add an identifier for that primitive to that queue).
Ellis et al., Bhiravabhatla et al., Lee et al., and Brigg et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the one or more processor cores are configured to form the batch of primitives to be rendered based on a queue allocated to a corresponding tile of the plurality of tiles reaching a capacity threshold, as taught by Brigg et al., to the Ellis et al. as modified by Bhiravabhatla et al. and Lee et al. system, because storing the primitive identifiers in the queues in the order in which they are received allows the ordering of the primitives within a region, and within a tile, to be maintained (paragraph 84 of Brigg et al.).
With respect to claim 13, Ellis et al. as modified by Bhiravabhatla et al., Lee et al., and Brigg et al. disclose the method of claim 12, as executed by the system of claim 7; see rationale for rejection of claim 7.
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stepuch et al. (U.S. PGPUB 20240169643) in view of Ellis et al. (U.S. PGPUB 20150062154) and further in view of Bhiravabhatla et al. (U.S. PGPUB 20240104684).
With respect to claim 15, Stepuch et al. disclose an acceleration unit (AU) (paragraph 174, FIG. 1 shows schematically a graphics processor 20), comprising:
a plurality of per-tile queues each allocated to a tile of a plurality of tiles of a frame to be rendered (paragraph 180, The tiling unit 52 determines the regions (tiles) of the render output that a primitive (at least partially) falls within (e.g. using a bounding box technique), and the primitive queuing unit 61 determines whether or not the primitive covers a number of regions of the render output that is less than or equal to the number of primitive queues (in the present embodiment, four)); and
one or more processor cores (paragraph 174, The graphics processor 20 includes a geometry processor 21) configured to: for each tile of the plurality of tiles: write geometry data of one or more primitives of the frame to be rendered at least partially visible in the tile in a per-tile queue of the plurality of per-tile queues allocated to the tile (paragraph 180, The tiling unit 52 determines the regions (tiles) of the render output that a primitive (at least partially) falls within (e.g. using a bounding box technique), paragraph 182, The primitive queue data stored includes the primitives that are written to the respective primitive queues (in accordance with the technology described herein) along with data indicating the respective regions of the render output to which the respective primitive queues are allocated). However, Stepuch et al. do not expressly disclose the processor core is configured to render, to one or more per-pixel color buffers (PPC buffers), pixel attribute data of the one or more primitives at least partially visible in the tile based on the geometry data of the one or more primitives at least partially visible in the tile stored in the per-tile queue allocated to the tile; and before determining lighting data for the primitives at least partially visible in the first tile, begin writing pixel attribute data of primitives at least partially visible in a second tile of the plurality of tiles.
Ellis et al., who also deal with tiled rendering, disclose a method for rendering, to one or more per-pixel color buffers (PPC buffers), pixel attribute data of the one or more primitives at least partially visible in the tile based on the geometry data of the one or more primitives at least partially visible in the tile stored in the per-tile queue allocated to the tile (paragraph 288, when processing a given tile, the graphics processing pipeline 1 is first controlled to render to respective separate render targets, the rendered geometry (G-buffers) required for the deferred shading operation. This processing pass may generate, for example, render targets for the tile comprising colour, depth, surface normals, and other attributes that are then stored separately in the tile buffer 10).
Stepuch et al. and Ellis et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method of rendering, to one or more per-pixel color buffers (PPC buffers), pixel attribute data of the one or more primitives at least partially visible in the tile based on the geometry data of the one or more primitives at least partially visible in the tile stored in the per-tile queue allocated to the tile, as taught by Ellis et al., to the Stepuch et al. system, because this can then reduce the amount of bandwidth and memory needed for particular processing operations in a tile-based graphics processing system (paragraph 298 of Ellis et al.).
Bhiravabhatla et al., who also deal with tiled rendering, disclose a method for before determining lighting data for the primitives at least partially visible in the first tile, begin writing pixel attribute data of primitives at least partially visible in a second tile of the plurality of tiles (paragraph 30, 1) a bin visibility pass (also referred to hereinafter as a binning pass) that includes streaming the geometry positions (e.g., vertices) into the GPU, where triangle level visibility tests may be performed and low resolution Z (LRZ) buffer and the visibility buffer may be primed, and then the triangles may be sorted into various bins with the visibility information recorded, paragraph 61, The results of the visibility check 404 may be the visibility data/LRZ buffer 414. The positions 412 and the visibility data/LRZ buffer 414 may be stored in the memory 450 (e.g., DDR/main memory), paragraph 62, the visibility data/LRZ buffer 416 and the positions/attributes 418, which may be stored in the memory 450, may correspond to the visibility data/LRZ buffer 414 and the positions 412 in the binning pipeline 430… The pixel pipeline 408 may perform per-pixel tests and operations (e.g., depth tests, pixel blending, etc.) and programmable shading and lighting before outputting the final color). Since Bhiravabhatla et al. disclose a bin visibility pass for sorting triangles into various bins, this includes at least a first and second tile. The positions/attributes are stored in memory 450 before shading and lighting before outputting the final color.
Stepuch et al., Ellis et al. and Bhiravabhatla et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method of before determining lighting data for the primitives at least partially visible in the first tile, begin writing pixel attribute data of primitives at least partially visible in the second tile, as taught by Bhiravabhatla et al., to the Stepuch et al. as modified by Ellis et al. system, because in a rendering pass, the primitives in each bin can be rendered separately. In these instances, the visibility stream can be fetched from memory used to drop primitives which are not visible for that bin (paragraph 53 of Bhiravabhatla et al.), thus improving system performance.
With respect to claim 16, Stepuch et al. as modified by Ellis et al. and Bhiravabhatla et al. disclose the AU of claim 15, wherein the one or more processor cores are configured to: for each tile of the plurality of tiles, based on the pixel attribute data of the one or more primitives at least partially visible in the tile, determine lighting data of the one or more primitives at least partially visible in the tile (Ellis et al.: paragraph 288, This processing pass may generate, for example, render targets for the tile comprising colour, depth, surface normals, and other attributes that are then stored separately in the tile buffer 10. (As is known in the art, when performing deferred shading, these values are then used to do complex light calculations and composition to produce the final desired output result.)).
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stepuch et al. (U.S. PGPUB 20240169643) in view of Ellis et al. (U.S. PGPUB 20150062154), Bhiravabhatla et al. (U.S. PGPUB 20240104684), and further in view of Hakura et al. (U.S. PGPUB 20180307490).
With respect to claim 17, Stepuch et al. as modified by Hakura et al. and Bhiravabhatla et al. disclose the AU of claim 15. However, Stepuch et al. as modified by Hakura et al. and Bhiravabhatla et al. do not expressly disclose the one or more processor cores are configured to: release, from the PPC buffers, pixel attribute data of one or more primitives at least partially visible in a first tile of the plurality of tiles; and concurrently with releasing the pixel attribute data of the one or more primitives at least partially visible in a first tile from the PPC buffers, render, to the PPC buffers, the pixel attribute data of one or more primitives at least partially visible in the second tile of the plurality of tiles.
Hakura et al., who also deal with tiled rendering, disclose a method wherein the one or more processor cores are configured to: release, from the PPC buffers, pixel attribute data of one or more primitives at least partially visible in a first tile of the plurality of tiles; and concurrently with releasing the pixel attribute data of the one or more primitives at least partially visible in a first tile from the PPC buffers, render, to the PPC buffers, the pixel attribute data of one or more primitives at least partially visible in the second tile of the plurality of tiles (paragraph 63, Once the graphics primitives associated with the first cache tile are processed by the screen space pipeline 354, the portion of the L2 caches associated with the first cache tile may be flushed and the tiling unit may transmit graphics primitives associated with a second cache tile).
Stepuch et al., Ellis et al., Bhiravabhatla et al., and Hakura et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the one or more processor cores are configured to: release, from the PPC buffers, pixel attribute data of one or more primitives at least partially visible in a first tile of the plurality of tiles; and concurrently with releasing the pixel attribute data of the one or more primitives at least partially visible in a first tile from the PPC buffers, render, to the PPC buffers, the pixel attribute data of one or more primitives at least partially visible in the second tile of the plurality of tiles, as taught by Hakura et al., to the Stepuch et al. as modified by Ellis et al. and Bhiravabhatla et al. system, because the overall memory traffic to the L2 caches and to the render targets may be reduced (paragraph 63 of Hakura et al.).
With respect to claim 18, Stepuch et al. as modified by Ellis et al., Bhiravabhatla et al., and Hakura et al. disclose the AU of claim 17, wherein the one or more processor cores are configured to: determine lighting data for the pixels of the one or more primitives at least partially visible in the first tile of the plurality of tiles based on the pixel attribute data of the one or more primitives at least partially visible in a first tile of the plurality of tiles (Hakura et al.: paragraph 76, Such configurations could include storage for various information, including, without limitation, 3D positional data, diffuse lighting information, and specular lighting information).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stepuch et al. (U.S. PGPUB 20240169643) in view of Ellis et al. (U.S. PGPUB 20150062154), Bhiravabhatla et al. (U.S. PGPUB 20240104684), and further in view of Dimitrov et al. (U.S. PGPUB 20150213638).
With respect to claim 19, Stepuch et al. as modified by Ellis et al. and Bhiravabhatla et al. disclose the AU of claim 15. However, Stepuch et al. as modified by Ellis et al. and Bhiravabhatla et al. do not expressly disclose the one or more processor cores are configured to: for each tile of the plurality of tiles, perform a scissor operation on pixels of the one or more primitives at least partially visible in the tile.
Dimitrov et al., who also deal with tiled rendering, disclose a method wherein the one or more processor cores are configured to: for each tile of the plurality of tiles, perform a scissor operation on pixels of the one or more primitives at least partially visible in the tile (paragraph 115, For each screen tile 704, and prior to the sub-draw-calls for that screen tile 704, the driver 103 transmits a scissor command to the graphics subsystem 500).
Stepuch et al., Ellis et al., Bhiravabhatla et al., and Dimitrov et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the one or more processor cores are configured to: for each tile of the plurality of tiles, perform a scissor operation on pixels of the one or more primitives at least partially visible in the tile, as taught by Dimitrov et al., to the Stepuch et al. as modified by Ellis et al. and Bhiravabhatla et al. system, because geometry that overlaps in screen space is tiled together, which reduces the number of cache misses and improves memory access time. Another advantage is that reducing cache misses reduces memory bandwidth consumption which helps to save power and increase processing speed (paragraph 132 of Dimitrov et al.).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stepuch et al. (U.S. PGPUB 20240169643) in view of Ellis et al. (U.S. PGPUB 20150062154), Bhiravabhatla et al. (U.S. PGPUB 20240104684), and further in view of Steiner et al. (U.S. Patent No. 8,537,168).
With respect to claim 20, Stepuch et al. as modified by Ellis et al. and Bhiravabhatla et al. disclose the AU of claim 15. However, Stepuch et al. as modified by Ellis et al. and Bhiravabhatla et al. do not expressly disclose the one or more processor cores are configured to: for each tile of the plurality of tiles, perform a depth-culling operating on pixels of the one or more primitives at least partially visible in the tile.
Steiner et al., who also deal with tiled rendering, disclose a method wherein the one or more processor cores are configured to: for each tile of the plurality of tiles, perform a depth-culling operating on pixels of the one or more primitives at least partially visible in the tile (column 6, lines 39-45, The depth cull component 505, sometimes referred to as the Z cull component, examines the tiles identified by the coarse raster component 503 and functions by discarding, or culling, the pixels comprising those portions of the graphics primitive that are covered by, or are otherwise included in, other graphics primitives).
Stepuch et al., Ellis et al., Bhiravabhatla et al., and Steiner et al. are in the same field of endeavor, namely computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the one or more processor cores are configured to: for each tile of the plurality of tiles, perform a depth-culling operating on pixels of the one or more primitives at least partially visible in the tile, as taught by Steiner et al., to the Stepuch et al. as modified by Ellis et al. and Bhiravabhatla et al. system, because generation of the combined coverage mask is subsequent to coarse rasterization, a number of bounding box tests, depth culling, window ID, and stipple operations. Each of the above operations typically function by turning off pixels (e.g., "killing pixels") which would otherwise be turned on due to their coverage by the graphics primitive. The concentration of a number of these pixel killing functions within the window ID unit 506 provides a number of advantages (column 8, lines 34-41 of Steiner et al.).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, and 15 have been considered but are moot in view of the new ground(s) of rejection.
Applicant's arguments filed June 18, 2026 have been fully considered but they are not persuasive. Applicant argues that Hakura does not disclose writing pixel attribute data for a second cache tile concurrently with flushing the first cache tile, and instead explicitly states that a tiling unit begins accepting primitives only after flushing the first cache tile (page 10 of remarks). However, the flush and transmit operations (paragraph 63, the portion of the L2 caches associated with the first cache tile may be flushed and the tiling unit may transmit graphics primitives associated with a second cache tile) in the context of such a system are performed substantially instantaneously, or concurrently. Furthermore, paragraph 95 is not relied upon in the Office Action and does not explicitly state that a tiling unit begins accepting primitives only after flushing the first cache tile.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. PGPUB 20130120380 to Kallio et al. for a method of performing binning prior to shading, blending, and illuminating.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW GUS YANG whose telephone number is (571)272-5514. The examiner can normally be reached M-F 9 AM - 5:30 PM.
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/ANDREW G YANG/Primary Examiner, Art Unit 2614
7/8/26
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