The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al (US 2022/0373748 A1).
Regarding claim 1, Chen discloses (Figs. 13 – 17 and 29; para. 0049 – 0065) an apparatus, comprising (see annotated Fig. 29 below):
an optical waveguide 12 (para. 0049);
a heater element 17 over the optical waveguide 12 (in the orientation of Fig. 29); and
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a dielectric material 16 (comprising 161,162,163,164) over and adjacent to heater element 17, wherein one or more voids 18 within the dielectric material 16 are over the heater element 17 (“the dielectric layer 16 is removed to form the upper first cavity 18” at para. 00065).
Annotated Fig. 29 of Chen.
Regarding claim 2, Chen teaches that the heater element 17 has a transverse width W17 (as identified in Fig. 14) and a longitudinal length (as seen in Fig. 13) and that the at least one void 18 spans at least a majority of the longitudinal length (as seen in Fig. 13; “In some embodiments, the first cavity 18 vertically covers the entire heater 17” at para. 0051).
Regarding claim 3, Chen teaches that a width W18 of an individual one of the voids 18 (as identified in Fig. 14) spans at least a majority of the transverse width W17 (“the width W18 of the first cavity 18 is substantially the same as a width W17 of the heater 17” at para. 0051).
Regarding claim 4, Chen teaches that the voids 18 comprise one void 18 (Figs. 13, 15, and 29) spanning the majority of the longitudinal length (Figs. 13 and 15; “In some embodiments, the first cavity 18 vertically covers the entire heater 17” at para. 0051) and having a transverse width W18 exceeding that (W17) of the heater element 17 (“In some embodiments, the width W18 of the first cavity 18 is at least substantially equal to or greater than the width W17 of the heater 17” at para. 0051, emphasis added).
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Doerr et al (US 10,209,539 B1)
Regarding claim 1, Doerr discloses (Fig. 5E; Abstract; 6:1 – 26) an apparatus, comprising (see annotated Fig. 5E below (flipped upside down)):
an optical waveguide 540;
a heater element 545 over the optical waveguide 540 (in the flipped upside-down orientation); and
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a dielectric material 525,510,500,530 (1:17 – 18; 4:57 – 67) over and adjacent to heater element 545, wherein one or more voids 515 within the dielectric material 525,510,500,530 are over the heater element 545.
Annotated Fig. 5E of Doerr (flipped upside down).
As an aside and relevant comment, it is also noted the limitation “above” is a relative spatial term (as noted at para. 022 of the instant specification), while no particular frame of reference is defined. As such, any structure can be flipped upside down by 180o, if needed to set/match spatial orientation and match the limitation “above”.
Claim 1 and 5 – 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Guerber et al (US 2026/0044026 A1)
Regarding claim 1, Guerber discloses (Figs. 1a – 1c, 2a, and 2b; Abstract; para. 0058 – 0079) an apparatus, comprising (see annotated Fig. 1a below):
an optical waveguide 11;
a heater element 12 over the optical waveguide 11 (in the orientation of Fig. 1a; “The modulator 1 comprises a waveguide 11 and a heater 12” at para. 0060); and
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a dielectric material 21,22 (“The two layers 21, 22 are for example of SiO2” at para. 0059) over and adjacent to heater element 12, wherein one or more voids 41 within the dielectric material 21,22 are over the heater element 12 (Figs. 1a and 1c).
Annotated Fig. 1a of Guerber.
Regarding claims 5 and 6, Guerber teaches that the one or more voids 41 are vertically spaced apart (by gap Z12 – Z41, as denoted in Fig. 1a) from the heater element 12 by no more than a 300 nm thickness of the dielectric material 21,22 (“the heater 12 is located, for example, at a height Z12 (or depth) of between 1 μm and 9 μm below the upper surface 210” at para. 0060; “Each trench 41 may have a depth Z41, measured from the upper surface 210 of the first layer 21, of between 100 nm and 1000 nm” at para. 0067). For example, Z12 = 1 mm and Z41 = 900 nm so that Z12 – Z41 = 1,000 – 900 = 100 nm.
Regarding claims 7 and 8, Guerber teaches (see annotated Fig. 1a provided above for claim 1) that the one or more voids 41 are first voids and that the apparatus 1 further comprises one or more second voids 42,43 within the dielectric material 21,22 and adjacent to a sidewall of the heater element 12, wherein the one or more second voids 42,43 adjacent to the sidewall of the heater element 12 comprise a pair of second voids (42 and 43), and wherein individual ones of the pair of second voids (42 and 43) are adjacent to opposite sidewalls of the heater element 12 (as seen in Figs. 1a and 2a).
Regarding claim 9, Guerber teaches that the second voids 42,43 comprise a plurality of elongate voids aligned end-to-end along a longitudinal length W41 (along the X axis, as identified in Fig. 2b) of one of the first voids 41 (“A different arrangement of the vias could allow the width of the upper trench 41 to be further extended until the upper trench 41 extends along the entire length of the heater 12” at para. 0071; “The side trenches 42, 43 advantageously extend at least along the entire length L.sub.12 of the heater 12 so as to minimise thermal leakage along the first direction X” at para. 0075).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Guerber.
Regarding claims 5 and 6, Chen teaches that the one or more voids 18 are vertically spaced apart from the heater element 17 by a distance D18 (as identified in Fig. 14) that is greater than zero (“A distance D18 between the first cavity 18 and the heater 17 measured along the Z direction is greater than zero” at para. 0051). Hence, Chen generally considers a range at least overlaps with the recited ranges and, hence, a prima facies case of obviousness exists (MPEP 2144.05). Furthermore, Guerber discloses (Figs. 1a – 1c, 2a, and 2b; Abstract; para. 0058 – 0079) an apparatus having essential structural features similar to those in Che and teaches that the one or more voids 41 are vertically spaced apart (by gap Z12 – Z41, as denoted in Fig. 1a) from the heater element 12 by no more than a 300 nm thickness of the dielectric material 21,22 (“the heater 12 is located, for example, at a height Z12 (or depth) of between 1 μm and 9 μm below the upper surface 210” at para. 0060; “Each trench 41 may have a depth Z41, measured from the upper surface 210 of the first layer 21, of between 100 nm and 1000 nm” at para. 0067). For example, Z12 = 1 mm and Z41 = 900 nm so that Z12 – Z41 = 1,000 – 900 = 100 nm.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the separation distance/gap D18 in Chen can be within the ranges exemplified by Guerber as a matter of suitable/workable ranges. It is also noted that (i) the range limits depend on a particular application (particular materials and their thermal conductivities, etc); that (ii) the instant application does not provide any criticality for the exact values of the recited range limits; that (iii) it has been held that discovering the optimum or workable ranges of prior art involves only routine skill in the art (In re Aller, 105 USPQ 233); and that (iii) it has been held that "A recognition in the prior art that a property is affected by the variable is sufficient to find the variable result-effective." In re Applied Materials', Inc., 692 F.3d 1289, 1297 (Fed. Cir. 2012). It is well settled that it would have been obvious for an artisan with ordinary skill to develop workable or even optimum ranges for result-effective parameters. In re Boesch, 617 F.2d 272, 276 (CCPA 1980); see also In re Woodruff, 919 F.2d 1575, 1577-78 (Fed. Cir. 1990). To this end, the Chen – Guerber combination regards the separation distance/gap between the one or more voids and the heater element as a result-effective parameter (efficiency of heat isolation).
Regarding claims 7 – 9, the Chen – Guerber combination teaches expressly or renders obvious all of the recited limitations, as detailed above for the rejections based on 35 USC 102 based on Guerber.
Regarding claim 10, the Chen – Guerber combination renders obvious that the (side) second voids 42,43 are (at least partially) spaced apart from the first voids 41 by the dielectric material 21,22, as shown in Figs. 1b, 3a, and 4a of Guerber. Furthermore, Chen teaches (para. 0051) that the void 18 can have the width W18 that is greater than, equal to, or smaller than the width W17 of the heater 17 (but wider than the waveguide width W12). In the latter case, the (side) second voids (suggested by Guerber) are (completely) spaced apart from the first (vertical) voids (17 in Chen and 41 in Guerber) by the (surrounding) dielectric material.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Guerber in view of Bovington (US 2022/0404649 A1).
Regarding claim 10, Guerber teaches that the (side) second voids 42,43 are (at least partially) spaced apart from the first voids 41 by the dielectric material 21,22, as shown in Figs. 1b, 3a, and 4a of Guerber. Furthermore, Bovington discloses (Figs. 1D, 2B, and 4F; Abstract; para. 0020 – 0030) an apparatus having essential structural features similar to those in Guerber and comprising: an optical waveguide 130; a heater element 140 over the optical waveguide; and a dielectric material over and adjacent to heater element, wherein one or more voids 150 are first voids and wherein the apparatus further comprises one or more second voids 160a,160b within a dielectric material 110,120 and adjacent to a sidewall of the heater element 140. The one or more second voids 160a,160b adjacent to the sidewall of the heater element 140 comprise a pair of second voids 160a,160b, and wherein individual ones of the pair of second voids 160a,160b are adjacent to opposite sidewalls of the heater element 140, wherein the second voids 160a,160b comprises a plurality of elongate voids 160a,160b aligned end-to-end along a longitudinal length of one of the first voids 150, and wherein the second voids 160a,160b are (completely) spaced apart from the first voids 150 by the dielectric material 110,120.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second voids 42,43 in Guerber can be configured in accordance with the teachings of Bovington to be (completely) spaced apart from the first voids 41 by the dielectric material 21,22 (by making the first voids 41 narrower). The motivation for completely separated first and second voids is that they can be filled with different gases (or have a vacuum) and thereby modify/concentrate the thermal flow generated by the heater (para. 0030 of Bovington).
Claims 11 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US 2025/0085472 A1) in view of Chen.
Regarding claim 11, Yu discloses (Figs. 1 – 3; Abstract; para.0014 – 0045) an apparatus 100 (optoelectronic module) comprising:
an electronic integrated circuit (EIC) 120 (“The first semiconductor device 120 is bonded to the photonic integrated circuit 110. In some embodiments, the first semiconductor device 120 is an electronic integrated circuit (EIC—e.g., a device without optical devices)” at para. 0023); and
a photonic integrated circuit (PIC) 110 (electrically) coupled (electrically and mechanically) to the (overlying) EIC 120 through a plurality of interconnects 115,129 formed within an interconnect layer 125 (“an photonic integrated circuit (PIC) 110” at para. 0015; an overlying interconnect structure 125” at para. 0023; also para. 0025).
Yu teaches that the PIC 120 comprises a layer 101 with optical components 103, such as an optical waveguide(s) and an optical modulator(s) (para. 0015), but does not detail their structural particulars. However, Chen discloses (Figs. 13 – 17 and 29; para. 0049 – 0065) a PIC comprising (see annotated Fig. 29 provided above for claim 1):
an optical waveguide 12 (para. 0049);
a heater element 17 over the optical waveguide 12 (in the orientation of Fig. 29); and
a dielectric material 16 (comprising 161,162,163,164) over and adjacent to heater element 17, wherein one or more voids 18 within the dielectric material 16 are over the heater element 17 (“the dielectric layer 16 is removed to form the upper first cavity 18” at para. 00065),
wherein the optical waveguide 12, the heater element 17, and the dielectric material 16 are comprised in an optical modulator (variable optical attenuator (VOA); para. 0027 and 0028).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the modulator of Chen can be comprised, as a drop-in component, within the layer 101 of the optoelectronic module of Yu in order to enable a modulation functionality in it, as intended by Yu (para. 0015).
In light of the foregoing analysis, the Yu – Chen combination teaches expressly or renders obvious all of the recited limitations.
Regarding claim 12, the Yu – Chen combination considers (Fig. 1B) an embodiment wherein the PIC 110 further comprises a metal-insulator-metal (MIM) capacitor 109 (formed by a pair of metal layers 104,106 that sandwich an insulator layer 108 therebetween) between a (upper horizontal) plane of the interconnects 125 and a second plane (lower place between 109 and 101) that is substantially parallel to the (horizontal) plane of the waveguide 103 (para. 0015 of Yu), and wherein the second plane passes between the MIM capacitor 109 and the voids (disposed within the layer 101, as part of the devices 103) (“In some embodiments the first metallization layers 107 can also include one or more first capacitors 109 within the first metallization layers 107 and electrically connected to conductive portions of the first metallization layers 107. In an embodiment the first capacitors 109 may be metal-insulator-metal (MIM) capacitors, super high performance metal-insulator-metal (SHP-MIM) capacitors, deep trench capacitors (DTC), stacked-capacitor (STC), combinations of these, or the like. In a particular embodiment in which the first capacitors 109 are MIM capacitors, each of the first capacitors 109 includes a lower metal layer 104, an upper metal layer 106 (e.g., copper layers) and a dielectric layer 108 (e.g., a high-k dielectric layer) between the metal layers” at para. 0018 of Yu, emphasis added).
Regarding claims 13 and 14, the Yu – Chen combination teaches expressly or renders obvious all of the recited limitations, as detailed above for the rejections of claims 2 – 4 under 35 USC 102 based on Chen.
Regarding claim 15, the Yu – Chen combination considers (Fig. 5 of Yu) an optical coupler 517 attached to the PIC 507 (“An optical fiber 517 is utilized as an optical input/output port to the interposer structure 500. In an embodiment the optical fiber 517 is placed so as to optically couple the optical fiber 517 and an optical input such as an edge coupler that is part of the third optical devices 503 within the fourth metallization layer 507” at para. 0067).
Regarding claim 16, the teachings of Yu and Chen combine (see the arguments and motivation for combining, as provided above for claim 11) to teach expressly or render obvious all of the recited step limitations of a corresponding method of making the contemplated PIC, as detailed above for claim 1. Specifically, the Yu – Chen combination considers a method, comprising:
receiving a PIC structure comprising (see annotated Fig. 29 of Chen provided above for claim 1) a dielectric material 16 (comprising 161,162,163,164) over a heater element 17 and an optical waveguide 12 (para. 0049);
forming a void 18 in the dielectric material 16 and over the heater element 17; and
forming one or more metallization levels (within the interconnect layer 125 and the layer 107, as shown in Fig. 1A of Yu; “FIG. 1A further illustrates that first metallization layers 107 are used in order to electrically connect the first active layer 101 of first optical components 103 to control circuitry, to each other, and to subsequently attached devices” at para. 0017) over the void 18 (disposed with the underlying layer 101 as one of the optical components 103; para. 0015 of Yu).
Alternatively or additionally, the teachings of Yu may be applied to illustrate a suitable/workable application of the optical modulator of Chen. The Chen – Yu combination provides an alternative ground of rejection.
Claims 17 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et in view of Yu, and further in view of Davies et al (US 2019/0369328 A1).
Regarding claim 17, Chen forms the void 18 above the heater 17 by a method that removes a portion of a deposited material 163,164 (step O106 in Fig. 17, as illustrated and detailed in Figs. 25 – 29), but Chen does not teach the deposited material can comprise a sacrificial material feature. However, Davies discloses (Figs. 3 – 6; Abstract; para. 0022 – 0040) a structure comprising an optical waveguide 404 and a void 408, wherein the void 408 by the processing steps of:
forming a sacrificial material feature 405 (as identified in the top 2 drawings in Fig. 4; “a sacrificial layer 405 … The sacrificial layer comprises a sacrificial material” at para. 0023);
forming dielectric material 402,403 over the sacrificial material feature 405 (as seen in Fig. 4; para. 0023);
forming an opening 407 through the dielectric material 402,403 and exposing a portion of the sacrificial material feature 405 (3 drawing in Fig. 4; para. 0024); and
removing the sacrificial material 405 with an etchant provided through the opening 407 (4th/bottom drawing in Fig. 4; “The intermediate structure is then etched 4002 by the use of a chemically selective wet etch introduced to the via 407 to create the waveguide structure 420. The wet etch preferentially etches the sacrificial material to form the etched sacrificial layer 415, such that the sacrificial material is removed from a region extending at least from the via 407 to beyond the waveguide ridge 404, leaving an air gap 408 between the lower cladding layer 413 and the substrate 406 in that region” at para. 0025, emphasis added).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the void in the structure of the Chen – Yu combination can be formed by using a sacrificial material feature that is etched through an opening in an overlying dielectric material, as a suitable/workable method that is expressly taught by Davies and has the advantage of leaving a relatively small opening (a relatively small opening 407 in Fig. 4 of Davies vs a larger opening 18 in Fig. 26 of Chen) to fill before overlying layers (including the interconnect layer 125 in Fig. 1B of Yu is formed) are disposed over the (sealed) void (within the layer 101 in Fig. 1B of Yu).
Regarding claim 18, the Chen – Yu – Davies combination considers that forming the sacrificial material feature comprises:
depositing a thickness of dielectric material (corresponding to the dielectric layers 163,164 in Fig. 25 of Chen) over the heater element 17
depositing (between the layers 163 and 164) a sacrificial material (corresponding to 405 in Fig. 4 of Davies) having a composition different than that of the dielectric material 163,164; and
and patterning the sacrificial material into the sacrificial material feature (by etching the sacrificial material through an opening formed in the layer 164, according to the step in the 3rd drawing in Fig. 4 of Davies).
Regarding claim 19, Chen teaches that the void 18 can have a width W18 exceeding a corresponding width of the heater element 17 and a length that spans a majority of a corresponding width of the heater element 17 (ad detailed above for claim 2 – 4). Since the void 18 of the Chen – Yu – Davies combination has the same dimensions as those of the (removed) sacrificial material feature, the Chen – Yu – Davies combination considers that the sacrificial material feature has a width exceeding a corresponding width of the heater element and a length that spans a majority of a corresponding width of the heater element.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et in view of Chen, in view of Davies, and further in view of Lin et al (US 2021/0294130 A1).
Regarding claim 20, while the Chen – Yu – Davies combination considers that the void 18 is sealed by being covered by a dielectric material 164 (as shown in Figs. 28 and 29 of Chen), the Chen – Yu – Davies combination does not explicitly illustrate a step of occluding the opening (through which the void was formed by etching, according to Davies) to leave the void in place of the sacrificial material. However, Lin discloses (Figs. 2 and 12 – 17; para. 0023 – 0032 and 0079 – 0085) an optical modulator 100 (para. 0018) that is comprised in PIC 1700 (Fig. 17) and includes a void 120 formed around a heater 118, the void 120 being etched through an opening 1104,1106 (as shown in Figs. 12 and 13; para. 0079 and 0080). Lin explicitly illustrates a step of occluding the opening (Fig. 15; para. 0083) by depositing a sealing layer 110 whose protrusions 110a,110b partially penetrate the opening 120a,120b and thereby occlude it (para. 0028).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the opening in the structure of the Chen – Yu – Davies combination can be occluded by a portion of a sealing layer disposed thereupon, as generally rendered obvious by the combination and explicitly illustrated by Lin, so that the void can be filled by a gas (or be vacuum-isolated) and sealed for better heat confinement/isolation, as intended by Chen (0064 and 0065 of Chen) and Lin (para. 0026, 0028, and 008).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,416,380 B1 Fig. 1
US 2023/0090619 A1 Figs. 2 – 15
US 6,031,957 Fig. 1
US 7,565,038 B2 Figs. 2 – 4
US 7,920,770 B2 Fig. 1f
US 6,983,086 B2 Figs. 5, 6
US 2015/0340273 A1 Fig. 8
US 11,953,628 B2 Fig. 1A
US 2021/0191163 A1 Figs. 1, 2
US 2025/0244526 A1 Fig. 1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT TAVLYKAEV whose telephone number is (571)270-5634. The examiner can normally be reached 10:00 am - 6:00 pm, Monday - Friday.
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/ROBERT TAVLYKAEV/Primary Examiner, Art Unit 2896
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