DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 6, 11 and 16.
Pending: 1-20.
Withdrawn: 11-20.
Election/Restrictions
Applicant’s election without traverse of Group I Claim 1-10 in the reply filed on 8/4/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Chen et al., US PG pub. 20130043598 A1.
Re: Independent Claim 1, Chen discloses a substrate (101, fig. 2A); the substrate (101, fig. 2A) including a semiconductor material (¶0010; silicon wafer);
a semiconductor component (105, fig. 2A) extending into the semiconductor material (¶0010; silicon wafer);
an interconnect region (115, fig. 2A) on the semiconductor component (105, fig. 2A); a top metal layer (top metal layer in N thickness, fig. 2A) on the interconnect region (115, fig. 2A) in electrical contact with the interconnect region (115, fig. 2A), wherein a portion of the top metal layer (top metal layer in N thickness, fig. 2A) includes a bond pad (160, fig. 2A), the bond pad (160, fig. 2A) having a top surface (surface of 160 in the bonding area 161, fig. 2A), a thickness and top surface edges (157, fig. 2A);
a protective dielectric layer (170, fig. 2A) on the top metal layer (top metal layer in N thickness, fig. 2A); and a protective dielectric layer opening (A, fig. 2A) over a portion of the bond pad (160, fig. 2A), wherein the protective dielectric layer (170, fig. 2A) has a protective dielectric layer (170, fig. 2A) overlap of the bond pad (160, fig. 2A) extending from the top surface edges (157, fig. 2A) of the bond pad (160, fig. 2A) towards a center of the bond pad (160, fig. 2A), the protective dielectric layer (170, fig. 2A) overlap of the bond pad (160, fig. 2A) being equal to or greater than twice the bond pad (160, fig. 2A) thickness (¶0020 and ¶0030).
Re: Claim 2, Chen disclose(s) all the limitations of claim 1 on which this claim depends. Chen further discloses: wherein the protective dielectric layer (170, fig. 2A) is a single dielectric layer (left side 170 a single dielectric layer) consisting of a dielectric layer selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, and aluminum oxide (¶0020).
Re: Claim 3, Chen disclose(s) all the limitations of claim 1 on which this claim depends. Chen further discloses: wherein the protective dielectric layer (170, fig. 2A) consists of a plurality of dielectric layers (both left and right side 170), the plurality of dielectric layers selected from the group consisting of silicon dioxide, silicon oxynitride, silicon nitride, silicon carbide, and aluminum oxide (¶0020).
Re: Claim 4, Chen disclose(s) all the limitations of claim 1 on which this claim depends. Chen further discloses: wherein a protective dielectric layer (170, fig. 2A) thickness is between half and twice the bond pad (160, fig. 2A) thickness.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen et al., US PG pub. 20130043598 A1; in view of Xie et al., CN 101106114 A.
Re: Claim 5, Chen discloses all the limitations of claim 1 on which this claim depends. Chen is silent regarding: wherein the protective dielectric layer (170, fig. 2A) is free of a bond pad (160, fig. 2A) undercut region.
Xie teaches in figure 2G the protective dielectric layer 207 is free of a bond pad 205 having a undercut region.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a undercut region since this can improve mechanical anchoring when forming the electrical bonding layer attached to the bonding region.
Claim(s) 6-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen et al., US PG pub. 20130043598 A1; in view of Huang US PG pub. 20050006790 A1.
Re: Independent Claim 6, Chen discloses a substrate (101, fig. 2A); the substrate (101, fig. 2A) including a semiconductor material (¶0010; silicon wafer);
a semiconductor component (105, fig. 2A) extending into the semiconductor material (¶0010; silicon wafer);
an interconnect region (115, fig. 2A) on the semiconductor component (105, fig. 2A); a top metal layer (top metal layer in N thickness, fig. 2A) on the interconnect region (115, fig. 2A) in electrical contact with the interconnect region (115, fig. 2A), wherein a portion of the top metal layer (top metal layer in N thickness, fig. 2A) includes a bond pad (160, fig. 2A), the bond pad (160, fig. 2A) having a top surface (surface of 160 in the bonding area 161, fig. 2A), a thickness, top surface edges (157, fig. 2A), and a sidewall angle (154, fig. 2A); a protective dielectric layer (170, fig. 2A) on the top metal layer (top metal layer in N thickness, fig. 2A); and a protective dielectric layer opening (A, fig. 2A) over a portion of the bond pad (160, fig. 2A),
wherein the protective dielectric layer (170, fig. 2A) has a protective dielectric layer (170, fig. 2A) overlap of the bond pad (160, fig. 2A) extending from the top surface edges (157, fig. 2A) of the bond pad (160, fig. 2A) towards a center of the bond pad (160, fig. 2A), the protective dielectric layer (170, fig. 2A) overlap of the bond pad (160, fig. 2A) being equal to or greater than the bond pad (160, fig. 2A) thickness.
Chen is silent regarding: the bond pad having a sidewall angle less than seventy-five degrees.
Huang teaches in figure 12 that the bonding pad 80 having a sidewall angle less than 90 degrees (¶0017).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a angle at the bonding pad since this can reduce occurrence of the electromigration phenomenon due to the overlarge turning angle and stress reduction at the pad edge.
Re: Claim 7, Chen and Huang discloses all the limitations of claim 6 on which this claim depends. Chen further discloses: wherein the protective dielectric layer (170, fig. 2A) is a single dielectric layer (left side 170 a single dielectric layer) consisting of a dielectric layer selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, and aluminum oxide (¶0020).
Re: Claim 8, Chen and Huang discloses all the limitations of claim 6 on which this claim depends. Chen further discloses: wherein the protective dielectric layer (170, fig. 2A) consists of a plurality of dielectric layers (both left and right side 170), the plurality of dielectric layers selected from the group consisting of silicon dioxide, silicon oxynitride, silicon nitride, silicon carbide, and aluminum oxide (¶0020).
Re: Claim 9, Chen and Huang discloses all the limitations of claim 6 on which this claim depends. Chen further discloses: wherein a protective dielectric layer (170, fig. 2A) thickness is between half and twice the bond pad (160, fig. 2A) thickness (¶0020 and ¶0030).
Claim(s) 10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen et al., US PG pub. 20130043598 A1; in view of Huang US PG pub. 20050006790 A1; further in view of Xie et al., CN 101106114 A.
Re: Claim 10, Chen and Huang discloses all the limitations of claim 6 on which this claim depends. Chen and Huang is silent regarding: wherein the protective dielectric layer (170, fig. 2A) is free of a bond pad (160, fig. 2A) undercut region.
Xie teaches in figure 2G the protective dielectric layer 207 is free of a bond pad 205 having a undercut region.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a undercut region since this can improve mechanical anchoring when forming the electrical bonding layer attached to the bonding region.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Perry US PG pub. 20030228756 A1”) Discloses a bond pad structure comprising two bond pads, methods of forming the bond pad structure, an integrated circuit die incorporating the bond pad structure, and methods of using the bond pad structure are provided. Each of the bond pads comprise stacked metal layers, at least one lower metal layer and an upper metal layer. When the two pads are connected by a conductive material, they function as a single pad. The lower metal layer of one of the bond pads forms an extension that extends beneath the upper metal layer of the other of the bond pad. The lower metal extension functions to block the etching of a dielectric layer that is put down over the upper metal layers and the underlying substrate, for example, during a passivation etch to form the bond pad opening, to protect the substrate from damage.
* (“Yamanoue et al., US PG pub. 20040084777 A1”) discloses a semiconductor substrate an insulating structure formed of a plurality of insulating films; an interconnection structure buried in the insulating structure and formed of a plurality of conducting layers; and a plurality of dummy patterns formed of the same conducting layer as the conducting layers forming the interconnection structure and buried in a surface side of the respective insulating films, and the dummy patterns near the interconnection structure are connected with each other through via portions. Thus, the insulating structure near the interconnection structure are reinforced, and the generation of cracks and peelings in the interfaces between the insulating films or in the inter-layer insulating films due to mechanical stresses or thermal stresses can be prevented.
* (“Burrell et al, US PG pub. 20050074959 A1”) discloses a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting-the bond pads to the Ni/Au pad metallization.
* (“Lin et al., US PG pub. 20080050909 A1”) discloses a barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.
* (“Lin et al., US PG pub. 20150364420 A1”) discloses an interconnect structure includes a base layer, a plurality of dielectric layers and a conductive structure. The base layer includes a conductive region. The plurality of dielectric layers are formed over the base layer. The plurality of dielectric layers includes a first dielectric layer and an etch stop layer under the first dielectric layer. The conductive structure includes a plug. The plug includes a central region and one or more footing regions. The footing regions are formed around the central region and formed at least partially in the first etch stop layer. A total width of the central region and one or more footing regions at a bottom level of the plurality of dielectric layers is at least about 5% more than a width of the central region at the bottom level of the plurality of dielectric layers.
* (“Vigna et al., US Patent 6489228 B1”) discloses a protection structure of metal, extending vertically and laterally to and along a predominant part of the periphery of an electronic component integrated underneath the pad region. The protection structure comprises a substantially annular region formed from a second metal layer and absorbing the stresses exerted on the pad during wire bonding. The annular region may be floating or form part of the path connecting the pad to the electronic component.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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