DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending.
3. This office action is in response to the Applicant’s communication filed 09/17/2025 in response to PTO Office Action mailed 06/17/2025. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
Response to Arguments
4. Applicant’s arguments filed 09/17/2025 have been fully considered but they are not persuasive. Applicant’s arguments are summarized as:
1) The present application discloses that multiple physical devices (e.g., state machine engines 14, chips, separate devices) may be arranged in a rank and may provide data to each other via the IR bus and process buffer interface 136. Application, paragraph 78. That is, in contrast to Brown, the present application allows for a rank of physical devices inclusive of the state machine engines 14 and not merely a rank of elements (e.g., state machine lattices 30) of a single state machine engine 14. In this manner, the recitations of the independent claims directed to both a primary device and a secondary device, as well as their interactions, are not present in Brown, since Brown appears (at best) to describe interconnectivity of elements of (at most) a primary device. Additionally, Applicant has reviewed Dlugosch and submits that Dlugosch cannot be read as overcoming these deficiencies of Brown with respect to the independent claims, since Dlugosch appears, at best, to similarly teach interconnectivity of elements of (at most) a primary device but not both a primary device and a secondary device, as well as their interactions, as recited in the independent claims. For at least these reasons, Applicant respectfully submits that Dlugosch and Brown, taken alone or in hypothetical combination, do not teach or suggest all of the recitations of independent claims 1, 8, and 14 and, thus, cannot support a prima facie case of obviousness with respect to these claims.
As per argument 1, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the present application allows for a rank of physical devices inclusive of the state machine engines 14 and not merely a rank of elements (e.g., state machine lattices 30) of a single state machine engine 14.) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dlugosch (US Pub. No. 2011/0307433 A1 hereinafter “Dlugosch” – IDS Submission) in view of Brown et al. (US Pub. No. 2013/0159671 A1 hereinafter “Brown” – IDS Submission).
Referring to claim 1, Dlugosch discloses a data analysis system (Dlugosch – Fig. 1 & par. [0024] disclose a hierarchical parallel machine 10.), comprising:
a primary device (Dlugosch – Fig. 1 & par. [0024] disclose a first finite state machine (FSM) engine 12 (bottom engine).); and
a secondary device coupled to the primary device to receive the data to be analyzed (Dlugosch – Fig. 1 & par. [0024, 0030, 0034] disclose a second finite state machine (FSM) engine 12 (top engine) coupled to the first finite state machine (FSM) engine 12 (bottom engine) to receive a raw data stream to be analyzed.).
Dlugosch fails to explicitly disclose the primary device, comprising: a first data buffer configured to receive data to be analyzed; a first state machine lattice comprising a first plurality of configurable elements configured to analyze at least a portion of the data as a first analysis and to output a result of the first analysis; and a first buffer interface configured to receive the at least a portion of the data from the first data buffer and to provide the at least a portion of the data to the first state machine lattice for analysis; and the secondary device coupled to the primary device to receive the data to be analyzed, wherein the secondary device comprises: a second data buffer configured to receive the data to be analyzed; a second state machine lattice comprising a second plurality of configurable elements configured to analyze at least a second portion of the data as a second analysis and to output a result of the second analysis; and a second buffer interface configured to receive the at least a second portion of the data from the second data buffer and to provide the at least a second portion of the data to the second state machine lattice for analysis.
Brown discloses the primary device (Brown – Fig. 9 & par. [0075] disclose a state machine engine 14.), comprising:
a first data buffer configured to receive data to be analyzed (Brown – Fig. 9 & par. [0076] disclose data buffers 132 are configured to receive and temporarily store data to be analyzed.); a first state machine lattice comprising a first plurality of configurable elements configured to analyze at least a portion of the data as a first analysis and to output a result of the first analysis (Brown – Figs. 2-5, 9 & par. [0028-0029, 0075] disclose a FSM lattice 30 having a plurality of programmable elements which include state machine elements (SMEs) 34, 36. Claim 1 discloses each of the programmable elements comprising: a data analysis element comprising a plurality of memory cells configured to analyze at least a portion of a data stream and to output a result of the analysis.); and a first buffer interface configured to receive the at least a portion of the data from the first data buffer and to provide the at least a portion of the data to the first state machine lattice for analysis (Brown – Fig. 9 & par. [0076] disclose data to be analyzed may be received at the bus interface 130 and transmitted to the FSM lattice 30 through a number of buffers and buffer interfaces. The IR bus and process buffer interface 136 may facilitate the transfer of data to the process buffer 134. The IR bus and process buffer interface 136 ensures that data is processed by the FSM lattice 30 in order. The IR bus and process buffer interface 136 may coordinate the exchange of data, timing information, packing instructions, etc. such that data is received and analyzed in the correct order. Generally, the IR bus and process buffer interface 136 allows the analyzing of multiple data sets in parallel through logical ranks of FSM lattices 30.);
wherein the secondary device comprises: a second data buffer configured to receive the data to be analyzed; a second state machine lattice comprising a second plurality of configurable elements configured to analyze at least a second portion of the data as a second analysis and to output a result of the second analysis; and a second buffer interface configured to receive the at least a second portion of the data from the second data buffer and to provide the at least a second portion of the data to the second state machine lattice for analysis (Brown – “The secondary device comprises: a second data buffer…, a state machine lattice…, and a second buffer interface…” is nothing but a duplication of “the primary device comprises: a first data buffer…, a first state machine lattice…, and a first buffer interface…”. The claim limitations do not produce a new and unexpected result since it is merely a repeat of the “the primary device comprises: a first data buffer…, a first state machine lattice…, and a first buffer interface…”, but with respect to a second portion of the data as a second analysis.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Brown’s teachings with Dlugosch’s techniques for the benefit of obtaining electronic devices with parallel finite state machines for pattern-recognition (Brown – Par. [0002]).
Referring to claim 2, Dlugosch and Brown disclose the data analysis system of claim 1, wherein the first state machine lattice comprises a third plurality of configurable elements configured to receive the result of the analysis from the first plurality of configurable elements (Brown – Figs. 2-5, 9 & par. [0028] disclose a FSM lattice 30 comprises an array of blocks 32. As will be described, each block 32 may include a plurality of selectively couple-able hardware elements (e.g., programmable elements and/or special purpose elements) that correspond to a plurality of states in a FSM. Similar to a state in a FSM, a hardware element can analyze an input stream and activate a downstream hardware element, based on the input stream.).
Referring to claim 3, Dlugosch and Brown disclose the data analysis system of claim 2, wherein the third plurality of configurable elements are configured to analyze at least a portion of the result of the analysis as a third analysis and to output a result of the third analysis (Brown – Figs. 2-5, 9 & par. [0028] disclose a FSM lattice 30 comprises an array of blocks 32. As will be described, each block 32 may include a plurality of selectively couple-able hardware elements (e.g., programmable elements and/or special purpose elements) that correspond to a plurality of states in a FSM. Similar to a state in a FSM, a hardware element can analyze an input stream and activate a downstream hardware element, based on the input stream. Claim 1 discloses each of the programmable elements comprising: a data analysis element comprising a plurality of memory cells configured to analyze at least a portion of a data stream and to output a result of the analysis.).
Referring to claim 4, Dlugosch and Brown disclose data analysis system of claim 3, comprising a third data buffer configured to receive the result of the third analysis (Brown – Fig. 9 & par. [0079] disclose once a result of interest is produced by the FSM lattice 30, match results may be stored in a match results memory 150. That is, a "match vector" indicating a match (e.g., detection of a pattern of interest) may be stored in the match results memory 150. The match result can then be sent to a match buffer 152 for transmission over the bus interface 130 to the processor 12.) from the third plurality of configurable elements (Brown – Figs. 2-5, 9 & par. [0028] disclose a FSM lattice 30 comprises an array of blocks 32. As will be described, each block 32 may include a plurality of selectively couple-able hardware elements (e.g., programmable elements and/or special purpose elements) that correspond to a plurality of states in a FSM. Similar to a state in a FSM, a hardware element can analyze an input stream and activate a downstream hardware element, based on the input stream. Claim 1 discloses each of the programmable elements comprising: a data analysis element comprising a plurality of memory cells configured to analyze at least a portion of a data stream and to output a result of the analysis.).
Referring to claim 5, Dlugosch and Brown disclose the data analysis system of claim 1, comprising a third data buffer configured to receive the result of the first analysis from the first plurality of configurable elements (Brown – Fig. 9 & par. [0079] disclose once a result of interest is produced by the FSM lattice 30, match results may be stored in a match results memory 150. That is, a "match vector" indicating a match (e.g., detection of a pattern of interest) may be stored in the match results memory 150. The match result can then be sent to a match buffer 152 for transmission over the bus interface 130 to the processor 12.).
Referring to claim 6, Dlugosch and Brown disclose the data analysis system of claim 1, comprising a host processor coupled to the primary device (Brown – Fig. 1 shows processor 12 coupled to state machine engine 14.), wherein the host processor is configured to receive the result of the first analysis from the first plurality of configurable elements (Brown – Fig. 9 & par. [0079] disclose once a result of interest is produced by the FSM lattice 30, match results may be stored in a match results memory 150. That is, a "match vector" indicating a match (e.g., detection of a pattern of interest) may be stored in the match results memory 150. The match result can then be sent to a match buffer 152 for transmission over the bus interface 130 to the processor 12.).
Referring to claim 7, Dlugosch and Brown disclose the data analysis system of claim 1, wherein each configurable element of the first plurality of configurable elements and the second plurality of configurable elements comprises a plurality of memory cells (Brown – Figs. 3-5 & par. [0033-0039] disclose the state machine elements 34, 36 in each GOT 60 comprises a plurality of memory cells 80.).
Referring to claims 8 and 14, note the rejections of claim 1 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 9, Dlugosch and Brown disclose the method of claim 8, comprising receiving the result from the first set of configurable elements of the state machine lattice at the buffer interface and outputting the result from the buffer interface (Brown – see Fig. 2 & par. [0023, 0031]).
Referring to claim 10, Dlugosch and Brown disclose the method of claim 9, comprising receiving the result from the buffer interface at a second data buffer of the primary device (Brown – see Fig. 2 & par. [0023, 0031]).
Referring to claim 11, Dlugosch and Brown disclose the method of claim 8, comprising receiving the result at a second set of configurable elements of the primary device (Brown – see Fig. 2 & par. [0023, 0031]).
Referring to claims 12 and 18, note the rejections of claim 6 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 13, Dlugosch and Brown disclose the method of claim 8, comprising transmitting the result as the second data to be analyzed from the primary device to the secondary device (Brown – Fig. 1 & par. [0030] disclose A first level of the hierarchy (such as one implemented by the first FSM engine 12 or first PRP 32) can perform processing directly on a raw data stream, for example. That is, the first FSM 12 or PRP 32 can generate an output data stream (e.g., an indication of a match or matches in the raw data stream) as a function of the raw data stream on input bus 16 or input bus 36, respectively. As shown in FIG. 1, a second level (such as one implemented by the second FSM engine 12 or second PRP 32) processes an output data stream from the first level. For example, the second FSM engine 12 receives an output data stream from the first FSM engine 12 (provided on output bus 18) and the second FSM engine 12 processes an output data stream of the first FSM engine 12.).
Referring to claim 15, note the rejections of claim 7 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 16, note the rejection of claims 2 and 3 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 17, Dlugosch and Brown disclose the system of claim 14, wherein the primary device comprises a data buffer configured to receive the result of the first analysis from the first state machine lattice (Brown – Fig. 9 & par. [0079] disclose once a result of interest is produced by the FSM lattice 30, match results may be stored in a match results memory 150. That is, a "match vector" indicating a match (e.g., detection of a pattern of interest) may be stored in the match results memory 150. The match result can then be sent to a match buffer 152 for transmission over the bus interface 130 to the processor 12.).
Referring to claim 19, Dlugosch and Brown disclose the system of claim 14, wherein the primary device comprises a data buffer configured to store the at least a portion of first data for subsequent transmission to the first state machine lattice (Brown – Fig. 9 & par. [0076] disclose data to be analyzed may be received at the bus interface 130 and transmitted to the FSM lattice 30 through a number of buffers and buffer interfaces. Data buffers 132 are configured to receive and temporarily store data to be analyzed.).
Referring to claim 20, note the rejections of claim 13 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571)270-7754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Dayton Lewis-Taylor/
Examiner, Art Unit 2181
/Farley Abad/ Primary Examiner, Art Unit 2181