DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/25/2026 has been entered.
Response to Amendment
The office action is responding to the amendments filed on 02/25/2026. Claims 1 and 9 have been amended. Claim 20 was previously cancelled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Navon et al. [US 2020/0409856 A1].
Regarding Claim 1, Navon teaches “A device comprising: at least one circuit configured to track a first utilization of a first set of cache entries of a cache;” as “According to a first aspect, a cache utilization manager is disclosed, configured to track cache utilization metrics of a mapping table cache based on a logical address” [¶0004]
“select a first replacement policy for the first set of cache entries in response to the tracking of the first utilization of that first set of cache entries of the cache apply the first replacement policy when performing cache entry replacement in the first set of cache entries;” as “A host may use a tuning parameter to adjust a cache eviction policy when a storage command is sent to the storage device 802 to change performance characteristics.” [¶0080] (This paragraph further recites, the device is tracking scores and based on the score the eviction plicy is changed.)
“track a second utilization of a second set of cache entries of the cache;” as “the utilization tracker 906 and comparator 908 may calculate or revise cache utilization metrics for the cache entries and associate a score or ranking for the cache entries in response to a request from the cache swap manager 904.” [¶0085]
“select a second replacement policy for the second set of cache entries in response to the tracking of the second utilization of that second set of cache entries of the cache; and apply the second replacement policy when performing cache entry replacement in the second set of cache entries. ” as “the utilization tracker 906 and comparator 908 may reference cache utilization metrics and/or scores or rankings that were calculated previously for the cache entries in response to a request from the cache swap manager 904. In this manner, the cache eviction candidate is determined based on cache utilization metrics.” [¶0085] and “As used herein, the terms “first,” “second,” etc. are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise.” [¶0119] (The tracking is happening for all cache entries, therefore, it covers both first and second cache entries)
Claim 9 is anticipated by Navon under the same rationale of anticipation by claim 1.
Claim 17 is anticipated by Navon under the same rationale of anticipation by claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 7-8, 10, 15-16, 18 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Navon et al. [US 2020/0409856 A1] in view of Kelley et al. [US 2021/0406145 A1].
Claim 2 is rejected over Navon and Kelley.
Navon does not explicitly teach wherein the at least one circuit is configured to track the first utilization and the second utilization at least in part by: maintaining a first counter to track the first utilization; and maintaining a second counter to track the second utilization.
However, Kelley teaches “wherein the at least one circuit is configured to track the first utilization and the second utilization at least in part by: maintaining a first counter to track the first utilization; and” as “in some embodiments, a configuration value is or includes a counter or a timer, or a threshold for the counter or timer, that is used in a predictive replacement cache policy.” [¶0022]
“maintaining a second counter to track the second utilization.” as “cache policy A may be disabled (0) or enabled (1), may be set to use first values (e.g., counters, thresholds, etc.) (0) or second values (1), etc.” [¶0060]
Navon and Kelley are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Navon and Kelley before him/her, to modify the teachings of Navon to include the teachings of Kelley with the motivation of testing of individual cache policies and/or configurations thereof can provide a characterization of cache performance that is not representative of actual cache performance due to the interaction of the combination of the two or more cache policies and/or configurations thereof. [Kelley, ¶0005]
Claim 7 is rejected over Navon and Kelley.
Navon does not explicitly teach wherein the cache corresponds to one of: an instruction cache; a level one data cache; a level two data cache; a level three data cache; an optimizer plus cache; or a branch target buffer.
However, Kelley teaches “wherein the cache corresponds to one of: an instruction cache; a level one data cache; a level two data cache; a level three data cache; an optimizer plus cache; or a branch target buffer.” as “cache policies are used for controlling the operation of one or more caches (e.g., L1 instruction cache 202, L1 data cache 204, L2 cache 206, and/or L3 cache parts 120-126 in FIG. 1) in an electronic device (e.g., electronic device 100 in FIG. 1).” [¶0021]
Navon and Kelley are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Navon and Kelley before him/her, to modify the teachings of Navon to include the teachings of Kelley with the motivation of testing of individual cache policies and/or configurations thereof can provide a characterization of cache performance that is not representative of actual cache performance due to the interaction of the combination of the two or more cache policies and/or configurations thereof. [Kelley, ¶0005]
Claim 8 is rejected over Navon and Kelley.
Navon does not explicitly teach wherein the second replacement policy is different from the first replacement policy.
However, Kelley teaches “wherein the second replacement policy is different from the first replacement policy.” as “Generally, for testing the combinations of two or more cache policies, the cache policy manager causes the cache controller to perform cache operations (e.g., storing copies of instructions and/or data in the cache, replacing copies of instructions and/or data in the cache, etc.) using different configurations of the combinations of two or more cache policies being tested. ” [¶0026]
Navon and Kelley are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Navon and Kelley before him/her, to modify the teachings of Navon to include the teachings of Kelley with the motivation of testing of individual cache policies and/or configurations thereof can provide a characterization of cache performance that is not representative of actual cache performance due to the interaction of the combination of the two or more cache policies and/or configurations thereof. [Kelley, ¶0005]
Claim 10 is rejected over Navon and Kelley under the same rationale of rejection of claim 2.
Claim 15 is rejected over Navon and Kelley under the same rationale of rejection of claim 7.
Claim 16 is rejected over Navon and Kelley under the same rationale of rejection of claim 8.
Claim 18 is rejected over Navon and Kelley under the same rationale of rejection of claim 2.
Claim 21 is rejected over Navon and Kelley.
Navon does not explicitly teach further comprising, independent of the first set of cache entries of the cache: monitoring, by the at least one physical processor, a second utilization of a second set of cache entries of the cache;
selecting, by the at least one physical processor, a replacement policy for the second set of cache entries, the replacement policy being the first replacement policy or another replacement policy; and
applying, by the at least one physical processor, the replacement policy when performing cache entry replacement in the second set of cache entries.
However Kelley teaches “further comprising, independent of the first set of cache entries of the cache: monitoring, by the at least one physical processor, a second utilization of a second set of cache entries of the cache;” as “a combination of two or more cache policies (e.g., replacement and write back/write through policies, etc.) and/or configurations thereof may be simultaneously in use in caches.” [¶0005] (Plurality of cache utilization policy is recited, which covers the second utilization)
“selecting, by the at least one physical processor, a replacement policy for the second set of cache entries, the replacement policy being the first replacement policy or another replacement policy; and” as “one or more configuration values control which replacement cache policy is in use in some or all of the caches.” [¶0022]
“applying, by the at least one physical processor, the replacement policy when performing cache entry replacement in the second set of cache entries.” as “In some embodiments, the testing of two or more configurations of combinations of two or more cache policies is performed simultaneously in separate test regions in the cache, possibly with a separate test region being used for each available configuration of the combination of two or more cache policies.” [¶0027]
Navon and Kelley are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Navon and Kelley before him/her, to modify the teachings of Navon to include the teachings of Kelley with the motivation of testing of individual cache policies and/or configurations thereof can provide a characterization of cache performance that is not representative of actual cache performance due to the interaction of the combination of the two or more cache policies and/or configurations thereof. [Kelley, ¶0005]
Claim(s) 3-6, 11-14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Navon et al. [US 2020/0409856 A1] in view of Kelley et al. [US 2021/0406145 A1] and in further view of Rohillah et al. [US 11,886,354 B1].
Claim 3 is rejected over Navon, Kelley and Rohillah.
The combination of Navon and Kelley does not explicitly teach wherein the at least one circuit is configured to select the first replacement policy and the second replacement policy at least in part by: selecting, in response to the first counter failing to meet a threshold condition, to continue to apply the first replacement policy to the first set of cache entries; and
selecting, in response to the second counter meeting the threshold condition, the second replacement policy for application to the second set of cache entries.
However, Rohillah teaches “wherein the at least one circuit is configured to select the first replacement policy and the second replacement policy at least in part by: selecting, in response to the first counter failing to meet a threshold condition, to continue to apply the first replacement policy to the first set of cache entries; and” as “in response to detecting that the value of the performance metric (e.g., hit rate) for the first cache does not meet a first threshold,” [Col 8, lines 11-13]
“selecting, in response to the second counter meeting the threshold condition, the second replacement policy for application to the second set of cache entries.” as “that the value of the performance metric for the second cache meets a second threshold,” [Col 8, lines 13-15]
Navon, Kelley and Rohillah are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Navon, Kelley and Rohillah before him/her, to modify the teachings of combination of Navon and Kelley to include the teachings of Rohillah with the motivation of workloads that have a working set greater than the available cache size, such a policy is susceptible to thrashing. In some embodiments, such workloads are often victim to being placed in the MRU position of a cache and being adjusted from the MRU position to the LRU position without ever receiving a cache hit. In such situations, the use of other insertion policies may advantageously mitigate thrashing. [Rohillah, Col 3, lines 10-17]
Claim 4 is rejected over Navon, Kelley and Rohillah.
The combination of Navon and Kelley does not explicitly teach wherein the threshold condition corresponds to at least one of: a threshold number of hits on a given set of cache entries; a threshold number of accesses of the given set of cache entries; or a threshold criticality of accesses of the given set of cache entries.
However, Rohillah teaches wherein the threshold condition corresponds to at least one of: a threshold number of hits on a given set of cache entries; a threshold number of accesses of the given set of cache entries; or a threshold criticality of accesses of the given set of cache entries.” as “One non-limiting example metric is hit rate, which may be tracked for multiple cache levels.” [Col 2, lines 14-15]
Claim 5 is rejected over Navon, Kelley and Rohillah.
The combination of Navon and Kelley does not explicitly teach wherein the at least one circuit is configured to select the first replacement policy and the second replacement policy at least in part by: dynamically switching, for an individual set of cache entries, from the first replacement policy to the second replacement policy in response to at least one of a hit rate or a replacement rate tracked for the individual set of cache entries meeting a threshold condition.
However, Rohillah teaches “wherein the replacement policy selection circuitry is configured to select the first replacement policy and the second replacement policy at least in part by: dynamically switching, for an individual set of cache entries, from the first replacement policy to the second replacement policy in response to at least one of a hit rate or a replacement rate tracked for the individual set of cache entries meeting a threshold condition.” as “ In some embodiments, cache controller circuitry 110 is configured to switch to a non-default insertion policy to mitigate cache thrashing only if prefetch coverage does not meet a threshold, e.g., in addition to hit rates for the first cache and second cache meeting or not meeting certain thresholds.” [Col 5, lines 29-34]
Navon, Kelley and Rohillah are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Navon, Kelley and Rohillah before him/her, to modify the teachings of combination of Navon and Kelley to include the teachings of Rohillah with the motivation of workloads that have a working set greater than the available cache size, such a policy is susceptible to thrashing. In some embodiments, such workloads are often victim to being placed in the MRU position of a cache and being adjusted from the MRU position to the LRU position without ever receiving a cache hit. In such situations, the use of other insertion policies may advantageously mitigate thrashing. [Rohillah, Col 3, lines 10-17]
Claim 6 is rejected over Navon, Kelley and Rohillah.
The combination of Navon and Kelley does not explicitly teach wherein the first replacement policy and the second replacement policy include: a static re-reference interval prediction replacement policy; and a least recently used replacement policy.
However, Rohillah teaches “wherein the first replacement policy and the second replacement policy include: a static re-reference interval prediction replacement policy; and a least recently used replacement policy.” as “ in response to the hit rate of first cache 120 not meeting a first threshold and the hit rate of second cache 130 meeting a second threshold over an interval (e.g., a set of cycles), insertion policy control 115 may change the insertion policy of first cache 120 from the MRU insertion policy to the LRU insertion policy for a subsequent interval.” [Col 3, lines 58-63]
Navon, Kelley and Rohillah are analogous arts because they teach storage system and cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Navon, Kelley and Rohillah before him/her, to modify the teachings of combination of Navon and Kelley to include the teachings of Rohillah with the motivation of workloads that have a working set greater than the available cache size, such a policy is susceptible to thrashing. In some embodiments, such workloads are often victim to being placed in the MRU position of a cache and being adjusted from the MRU position to the LRU position without ever receiving a cache hit. In such situations, the use of other insertion policies may advantageously mitigate thrashing. [Rohillah, Col 3, lines 10-17]
Claim 11 is rejected over Navon, Kelley and Rohillah under the same rationale of rejection by claim 3.
Claim 12 is rejected over Navon, Kelley and Rohillah under the same rationale of rejection by claim 4.
Claim 13 is rejected over Navon, Kelley and Rohillah under the same rationale of rejection by claim 5.
Claim 14 is rejected over Navon, Kelley and Rohillah under the same rationale of rejection by claim 6.
Claim 19 is rejected over Navon, Kelley and Rohillah under the same rationale of rejection by claim 3.
Response to Arguments
Applicant’s arguments with respect to amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/Primary Examiner, Art Unit 2132
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