DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
IDS filed on 5/8/2025,
Claims and remarks filed on 9/8/2025.
Withdrawn objections and rejections
The specification objection has been withdrawn.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (U.S. 2022/0137963), in view of Official Notice.
As per claim 1:
Yang disclosed an apparatus comprising:
circuitry (Yang: Figure 1 element 10, paragraph 20) configured to:
send a data value having a first data format to an accelerator of a plurality of accelerators (Yang: Figures 1 and 4 elements 12, 130, and 150, paragraphs 22, 28, 30, 37, 47-50, and 52-53)(The external memory sends data values to the type conversion data mover (i.e. first accelerator) for selective conversion between data formats. The internal type converter (i.e. second accelerator) also performs type conversion.), each physically distinct from and operable concurrently with a parallel data processing circuit (Yang: Figure 1 elements 130, 150, and 160, paragraphs 28 and 30-32)(The Polymorphic operator array (i.e. parallel data processing circuit) performs matrix operations that are physically distinct from the conversion operations done by the type converters (i.e. accelerators) using separate circuitry. The converters are configured to operate in parallel with the polymorphic operator array, but Yang doesn’t explicitly describe instances of parallel operation of these elements. Official notice is given that memory operations can be fetched from external memory to internal memory in parallel with execution units operating for the advantage of increased performance. Official notice is given that data fetches from caches can be pipelined and performed in parallel with execution units operating for the advantage of increased performance. Thus, it would have been obvious to one of ordinary skill in the art that the converters of Yang operate in parallel with the polymorphic operator array performing calculations.); and
send, to the accelerator, a first indication to cause circuitry of the accelerator (Yang: Figure 1 elements 110 and 130, paragraph 26)(The instruction analyzer determines changes in precision needed by an instruction and controls the type conversion data mover to perform a given conversion.) to:
replace the first data format of the data value with a second data format different from the first data format of the data value (Yang: Figures 1 4, and 6 elements 130 and S204, paragraphs 28, 48, 50-54, and 69)(The type conversion data mover performs a down conversion of input data from external memory.); and
store the data value with the second data format in a memory to be accessed by the parallel data processing circuit during execution of a data model (Yang: Figures 1 4, and 6 elements 130 and S204, paragraphs 23, 28, 48, 50-54, and 69)(The type conversion data mover performs a down conversion of input data from external memory. The result is stored in the internal memory that is accessed by the polymorphic operator array during neural network model (i.e. data model) processing.).
As per claim 2:
Yang disclosed the apparatus as recited in claim 1, wherein the circuitry is further configured to allow the data value with the second data format to be overwritten in the memory, responsive to receiving a second indication specifying that the parallel data processing circuit has completed accessing the data value with the second data format (Yang: Figure 1 elements 140 and 160, paragraphs 28, 31, and 37)(The internal memory stores outputs from the type conversion data mover. The polymorphic operator array uses the stored data as inputs for matrix processing, which is later stored in the internal memory. Official notice is given that memory structures can use a least recently used model to overwrite cached data for the advantage of overwriting data that isn’t likely to be used. Thus, it would have been obvious to one of ordinary skill in the art to implement such overwriting in the internal memory. After the processing result from the polymorphic operator array is stored in internal memory, the converted input data is overwritten when it reaches a least recently used status and memory capacity for new conversions or processing outputs is requested.).
As per claim 3:
Yang disclosed the apparatus as recited in claim 1, wherein:
the data model is a machine learning data model (Yang: Figure 1 element 100, paragraph 23); and
the data value is one of a weight value, an activation value and a gradient value (Yang: Figures 1 and 4 elements 12 and 130, paragraphs 3, 23, 28, and 31-32)(Official notice is given that neural networks process matrix operations using input activations and weight values for the advantage of performing training or inference operations. Thus, it would have been obvious to one of ordinary skill in the art that the input values being converted are weight and/or activation values.).
As per claim 4:
Yang disclosed the apparatus as recited in claim 2, wherein the circuitry is further configured to select the second data format based on a memory address range of a memory storage location storing the data value (Yang: Figure 1 elements 12, 110, and 130, paragraphs 26 and 28)(The data mover receives operation data for adjusting precision data. Official notice is given that load operations can gather a range of data from memory for the advantage of reducing the number of load operations to gather a set of data. Thus, it would have been obvious to one of ordinary skill in the art that the operations adjusting precision on input data load a range of input data from memory.).
As per claim 5:
Yang disclosed the apparatus as recited in claim 3, wherein the circuitry is further configured to send the first indication to the accelerator based on one or more of monitored activity levels of the plurality of accelerators and sizes of arrays being processed by the machine learning data model (Yang: Figure 1 elements 110 and 130, paragraph 26)(The instruction analyzer determines changes in precision needed by an instruction and controls the type conversion data mover to perform a given conversion. Official notice is given that schedulers can be aware of if execution circuits are currently in use prior to issuing instructions to them for the advantage of ensuring correct processing results. Thus, it would have been obvious to one of ordinary skill in the art to implement a scheduler in Yang that is aware of processing loads on the converters and operator array.).
As per claim 6:
Yang disclosed the apparatus as recited in claim 2, wherein the plurality of accelerators comprises one or more of a processing-in-memory (PIM) accelerator, a direct memory access (DMA) circuit and a digital signal processing circuit (DSPs) (Yang: Figure 1 elements 130 and 150, paragraph 28).
As per claim 7:
Yang disclosed the apparatus as recited in claim 3, wherein the second data format has less precision than the first data format (Yang: Figures 1 4, and 6 elements 130 and S204, paragraphs 28, 48, 50-54, and 69)(The type conversion data mover performs a down conversion of input data from external memory.).
As per claim 8:
Claim 8 essentially recites the same limitations of claim 1. Therefore, claim 8 is rejected for the same reasons as claim 1.
As per claim 9:
The additional limitation(s) of claim 9 basically recite the additional limitation(s) of claim 2. Therefore, claim 9 is rejected for the same reason(s) as claim 2.
As per claim 10:
The additional limitation(s) of claim 10 basically recite the additional limitation(s) of claim 3. Therefore, claim 10 is rejected for the same reason(s) as claim 3.
As per claim 11:
The additional limitation(s) of claim 11 basically recite the additional limitation(s) of claim 4. Therefore, claim 11 is rejected for the same reason(s) as claim 4.
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 5. Therefore, claim 12 is rejected for the same reason(s) as claim 5.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 6. Therefore, claim 13 is rejected for the same reason(s) as claim 6.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 7. Therefore, claim 14 is rejected for the same reason(s) as claim 7.
As per claim 15:
Claim 15 essentially recites the same limitations of claim 1. Claim 15 additionally recites the following limitations:
send a data value having a first data format from the memory to a first accelerator (Yang: Figures 1, 4, and 7 elements 12, 130-150, and S302, paragraphs 22, 28, 30, 37, 47-50, 52-53, and 77)(The external memory sends data values to the type conversion data mover (i.e. first accelerator) for selective conversion between data formats. During subsequent layer processing with needed conversions, output data stored in the internal memory is sent to the type conversion data mover for down conversion.).
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 2. Therefore, claim 16 is rejected for the same reason(s) as claim 2.
As per claim 17:
The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claim 3. Therefore, claim 17 is rejected for the same reason(s) as claim 3.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 4. Therefore, claim 18 is rejected for the same reason(s) as claim 4.
As per claim 19:
Yang disclosed the computing system as recited in claim 17, wherein the circuitry is further configured to send the first indication to the first accelerator based on one or more of types of operations being performed by the parallel data processing circuit (Yang: Figure 1 elements 110 and 130, paragraph 26)(The instruction analyzer determines changes in precision needed by an instruction and controls the type conversion data mover to perform a given conversion. Official notice is given that schedulers can be aware of if execution circuits are currently in use prior to issuing instructions to them for the advantage of ensuring correct processing results. Thus, it would have been obvious to one of ordinary skill in the art to implement a scheduler in Yang that is aware of processing loads on the converters and operator array.) and available capacity of the memory (Yang: Figure 1 elements 110 and 130, paragraph 26)(The instruction analyzer determines changes in precision needed by an instruction and controls the type conversion data mover to perform a given conversion. Official notice is given that schedulers can be aware of memory capacity for the advantage of ensuring read/write operations don’t exceed capacity. Thus, it would have been obvious to one of ordinary skill in the art to implement a scheduler in Yang that is aware of memory capacity.).
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 6. Therefore, claim 20 is rejected for the same reason(s) as claim 6.
Response to Arguments
The arguments presented by Applicant in the response, received on 9/8/2025 are partially considered persuasive.
Applicant argues for claims 1, 8, and 15:
“The above disclosures and Figure 1 of Yang describe the data mover 130 and the converter 150 perform a type conversion of data prior to the polymorphic operator array 160 receiving data to perform a matrix operation. The interface 120 "receive(s) an instruction or operation data to be processed by the neural network accelerator 100" and the elements 130 and 150 perform type conversion of data for the instruction prior to the polymorphic operator array 160 performing the operation of the instruction such as a matrix operation. The elements 130 and 150 are within the neural network accelerator 100 that also includes the polymorphic operator array 160, so the elements 130 and 150 are not physically distinct from the polymorphic operator array 160.”
This argument is not found to be persuasive for the following reason. The type conversion data mover, internal type converter, and the polymorphic operator array are clearly all physically distinct logic elements within the neural network accelerator. The type conversion and internal type converter perform data type conversions as needed based on neural network layer data input/output needs. This is clearly physically distinct from the polymorphic operator array performing addition, multiplication, and MAC operations. Thus, Yang reads upon the newly claimed limitation.
Applicant argues for claims 1, 8, and 15:
“Additionally, the elements 130 and 150 are not operable concurrently with the polymorphic operator array 160. The type conversion of data has to occur prior to the polymorphic operator array 160 performing the matrix operation. Therefore, each of the external memory 12, the data mover 130, and the converter 150 fails to disclose or suggest the claim 1 features "an accelerator of a plurality of accelerators, each physically distinct from and operable concurrently with a parallel data processing circuit." Accordingly, Yang fails to disclose or suggest the claim 1 features "circuitry configured to . . . send a data value having a first data format to an accelerator of a plurality of accelerators, each physically distinct from and operable concurrently with a parallel data processing circuit." For at least all of the above reasons, claim 1 is patently distinguishable from Yang.”
This argument is partially found to be persuasive for the following reason. Elements 130, 150, and 160 are configured to perform operations concurrently. However, Yang doesn’t explicitly cite instances of parallel operations of these elements. Thus, a new ground of rejection has been given due to the amendment.
Applicant argues for claims 1, 8, and 15:
“Providing results to the polymorphic operator array 160 of the neural network accelerator 100 fails to disclose or suggest "store the data value with the second data format in a memory to be accessed by the parallel data processing circuit during execution of a data model." As shown earlier, the recited parallel data processing circuit is separate from the recited apparatus. For at least these further reasons, claim 1 is patently distinguishable from Yang.”
This argument is not found to be persuasive for the following reason. The type conversions that are performed on input data are stored in the internal memory. These data elements are subsequentially sent to the polymorphic operation array for execution. Thus, reading upon the claimed limitation.
Applicant argues for claims 2, 9, and 16:
“Using a least-recently-used (LRU) technique provides delay before data removal from the memory such as the capacity of the memory or portion of the memory (set of a set-associative cache) needs to be filled first to cause the LRU metadata to be checked. Following, the corresponding LRU value needs to indicate replacement. Such a replacement policy fails to disclose or suggest “responsive to receiving a second indication specifying that the parallel data processing circuit has completed accessing the data value with the second data format.” Therefore, for at least these further reasons, claim 2 is patentably distinguishable from the cited art. Claims 9 and 16 include similar features and are similarly patentably distinguishable.”
This argument is not found to be persuasive for the following reason. In view of the official notice taken, the completed data is allowed to be overwritten when reaching a LRU status. The writing of completed data in the internal memory is the second indication. The overwriting is then responsive to both the completed data being written to the internal memory and reaching a LRU status. Thus, reading upon the claimed limitation.
Applicant argues for claims 4, 11, and 18:
“On pages 6-7 of the present Office Action, it is suggested that Yang generally discloses gathering a range of data and it is obvious that "the operations adjusting precision on input data load a range of input data from memory." However, generally loading a range of data is not equivalent to "select the second data format based on a memory address range of a memory storage location storing the data value." Therefore, for at least these further reasons, claim 4 is patentably distinguishable from the cited art. Claims 11 and 18 include similar features and are similarly patentably distinguishable.”
This argument is not found to be persuasive for the following reason. The official notice take allows for loading data to the internal memory based on a range of data addresses. This allows for performing the type conversion based on the various data types stored in external memory at the range of data addresses. Thus, reading upon the claimed limitations.
Applicant argues for claims 5, 12, and 19:
“On page 7 of the present Office Action, it is suggested that Yang generally discloses scheduling and "schedulers can be aware of if execution circuits are currently in use." However, generally being aware that an execution unit is in use is not equivalent to the further features of claim 5. Therefore, for at least these further reasons, claim 5 is patentably distinguishable from the cited art. Claims 12 and 19 include similar features and are similarly patentably distinguishable.”
This argument is not found to be persuasive for the following reason. The official notice taken allows for schedulers to be implemented that determines if circuits are currently in use. This allows for sending instructions to load data from external memory to internal memory with data conversions as needed based on current loading of data. Thus, reading upon the claimed limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183