Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 requires “wherein the destination register of the operation targets a different register than a destination register of the load instruction of the fused load instruction sequence.” Which appears to lack support in the original disclosure. While register renaming is discussing in [0035] it merely notes that “In some implementations, registers can be mapped (e.g., at rename stage 238) to different physical registers as needed” which describes a typical renaming functionality but this does not mean that the register must be different in all cases and is only limited to the physical register whereas the claim could read on both physical and logical registers. Examiner suggests cancelling the claim or aligning the limitation with the specification as disclosed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 4-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raja, US Pub No. 2021/0294607.
As to claim 1, Raja teaches: A device comprising (FIG. 1, data progressing apparatus 2):
a control circuit configured to (FIG. 1, processing circuitry 4):
generate, based on a first load instruction sequence, a second load instruction sequence having a number of load instructions that is greater than a number of load instructions of the first load instruction sequence ([0060] “the processing circuitry is configured to crack [generate] the plural-register-load instruction [first load instruction sequence] into the plurality of load operations [second load instruction sequenced] to be issued as separate load operations”) wherein the first load instruction sequence includes an operation applied to a destination register for the first load instruction sequence ([0060] “…data to be loaded to each of the destination registers of the plural-register load instruction [first load instruction sequence]…”); and
replace the first load instruction sequence with the second load instruction sequence in an instruction pipeline (FIG. 9).
As to claim 2, Raja teaches: The device of claim 1, wherein generating the second load instruction sequence includes converting a load instruction for contiguous memory locations in the first load instruction sequence into separate load instructions for the contiguous memory locations ([0058] “…addresses of contiguous blocks of address space…”, FIG. 9).
As to claim 4, Raja teaches: The device of claim 1, wherein replacing the first load instruction sequence with the second load instruction sequence further comprises replacing the first load instruction sequence with the second load instruction sequence in an operation cache ([0096] “retaining issued instructions or micro-operations in an issue queue 112 [operation cache]”).
As to claim 5, Raja teaches: The device of claim 1, wherein replacing the first load instruction sequence with the second load instruction sequence further comprises:
storing the second load instruction sequence in an operation cache that stores the first load instruction sequence to decode a load macro-operation ([0096] “retaining issued instructions or micro-operations in an issue queue 112 [operation cache]”); and
selecting the second load instruction sequence when decoding the load macro-operation (FIG. 9, step 174).
As to claim 6, Raja teaches: The device of claim 1, wherein the control circuit is further configured to replace the first load instruction sequence with the second load instruction sequence in response to a performance-based trigger (FIG. 9, step 172, cracked path, [0147] “Other systems may support dynamic selection of whether non-cracked mode or the cracked mode is used, for example based on the bandwidth available [performance-based trigger]”).
As to claim 7, Raja teaches: The device of claim 6, wherein the performance-based trigger corresponds to a load-store unit (LSU) utilization rate being below an LSU utilization rate threshold and a micro-operation dispatch rate exceeding a micro-operation dispatch rate threshold ([0148] “if the number of total load operations (including single loads and load pairs) includes more than a certain threshold fraction of load pair instructions then the cracked mode could be selected”).
As to claim 8, Raja teaches: The device of claim 6, wherein the performance-based trigger corresponds to a distribution of load sources ([0148] and [0149], FIG. 16).
As to claim 9, Raja teaches: The device of claim 6, wherein the performance-based trigger corresponds to a memory traffic for a memory controller satisfying a memory traffic threshold ([0148] and [0149], FIG. 16).
As to claim 10, Raja teaches: The device of claim 1, wherein the first load instruction sequence corresponds to a scalar (FIG. 4, #addX, #addX+4 showing two data elements, each a scalar value – note the claims are open ended by the use of ‘comprising’ and do not preclude more than one scalar value).
As to claim 11, Raja teaches: The device of claim 1, wherein the first load instruction sequence corresponds to a vector (FIG. 4, #addX, #addX+4 showing two data elements, i.e., vector).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raja as applied to claims 1, 2, and 4-11 above, and further in view of Chaudhry et al, US Pub No. 2007/0226463.
As to claim 3, Raja teaches: The device of claim 1.
Raja does not explicitly teach: wherein the control circuit is configured to replace the first load instruction sequence with the second load instruction sequence before a decode stage of the instruction pipeline. Raja does the replacement at the decode and issue stage specifically ([0060]). However, Chaudhry teaches using a pre-decode stage and, in that stage, replacing instructions ([0045]) in order to help the pipeline processing. The combination would have Raja include a pre-decode stage and shift the replacement to that stage. One of ordinary skill in the art would appreciate reducing stalls at the decode stage and improving overall pipeline efficiency by identifying and replacing instructions outside the normal flow of the pipeline.
Therefore, it would have been obvious before the effective filing date of the claimed invention to include a pre-decode stage and shift replacement to that stage of the pipeline. One would have been motivated to improve the throughput and flow of the pipeline.
Claim(s) 12, 14-16, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raja as applied to claims 1, 2, and 4-11 above, and further in view of Fulton, US Pub No. 2009/0077355.
As to claim 12, Raja teaches: A system (FIG. 7) comprising:
a memory (FIG. 7, memory 136);
a processor (FIG. 7, data progressing apparatus 2) having a plurality of registers (FIG. 7, registers 106); and
a control circuit (FIG. 7, processing circuitry 4) configured to:
identify a fused load instruction sequence for the plurality of registers that includes a load instruction for loading from multiple memory locations (FIG. 9, step 170) and an operation applied to a destination register of the fused load instruction (FIG. 9, step 170, [0060] “…data to be loaded to [applied to] each of the destination registers of the plural-register load instruction [first load instruction sequence]…”);
generate a split load instruction sequence by converting the load instruction into separate load instructions for each of the multiple memory locations into respective registers of the plurality of registers (FIG. 9, step 174, [0060] “the processing circuitry is configured to crack [generate] the plural-register-load instruction [load instruction] into the plurality of load operations [split load instruction] to be issued as separate load operations”); and
replace the fused load instruction sequence with the split load instruction sequence (FIG. 9, step 174).
Raja does not explicitly teach: wherein the operation is converted into a no-operation instruction. Raja does not specifically discuss what happens with replacement instructions. However, Fulton teaches the use of no-op replacement instructions as a means to ensure one-for-one instructions ([0035]) to prevent inadvertent jumping ([0036] “If multiple instructions are replaced, the instructions preferably should be executed as a single series so that code does not jump to the middle of the series. In many cases, a one-for-one instruction replacement is therefore likely”). The combination would have Raja include no-ops as part of the replacement to replace any instructions in the sequence not directly transferred into separate loads. One of ordinary skill in the art would appreciate preventing inadvertent jumping to ensure execution integrity that could come from issuing an instruction out of turn or otherwise introducing pipeline bubbles.
Therefore, it would have been obvious before the effective filing date of the claimed invention to include no-op instructions as in Fulton with the system of Raja. One would have been motivated to ensure execution integrity.
As to claim 14, Raja/Fulton teaches: The system of claim 12, wherein replacing the fused load instruction sequence with the split load instruction sequence further comprises replacing the fused load instruction sequence with the split load instruction sequence as an entry for a load macro-operation in an operation cache (Raja [0096] “retaining issued instructions or micro-operations in an issue queue 112 [operation cache]”).
As to claim 15, Raja/Fulton teaches: The system of claim 12, wherein replacing the fused load instruction sequence with the split load instruction sequence further comprises:
storing the split load instruction sequence in an operation cache that stores the fused load instruction sequence to decode a load macro-operation (Raja [0096] “retaining issued instructions or micro-operations in an issue queue 112 [operation cache]”); and
selecting the split load instruction sequence when decoding the load macro-operation (Raja FIG. 9, step 174).
As to claim 16, Raja/Fulton teaches: The system of claim 12, wherein the control circuit is further configured to replace the fused load instruction sequence with the split load instruction sequence in response to a performance-based trigger corresponding to at least one of:
a load-store unit (LSU) utilization rate being below an LSU utilization rate threshold;
a micro-operation dispatch rate exceeding a micro-operation dispatch rate threshold;
a distribution of load sources; or
a memory traffic for a memory controller satisfying a memory traffic threshold (Raja FIG. 9, step 172, cracked path, [0147] - [0149]).
As to claim 21, Raja/Fulton teaches: The system of claim 12, wherein the destination register of the operation targets a different register than a destination register of the load instruction of the fused load instruction sequence (Raja [0096] “a register rename stage 104 for mapping architectural register specifiers specified by the instructions to physical registers 106 provided in hardware”, using the register renaming table would mean a different physical destination register).
Allowable Subject Matter
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art of record does not explicitly teach detecting, in an instruction pipeline, a first load instruction sequence for a plurality of registers that includes a load instruction for loading a target load from contiguous memory locations and a shift instruction for loading a desired portion of the target load into a desired register of the plurality of registers; converting the load instruction into separate load instructions for loading each of the contiguous memory locations into respective registers of the plurality of registers; removing the shift instruction in a second load instruction sequence that includes the separate load instructions in view of the rest of the limitations of claim 17. Specifically, while the closest prior art of record, Raja, discloses replacing instructions with plural instructions it does not detail the inclusion of a shift instruction as part of the original sequence nor its removal in the context of replacing the load instruction. Being that the instruction itself is removed there’d be no clear motivation to add it into the original instructions in Raja absent hindsight reasoning. Claims 18-20 depend from claim 17 and are thus allowed for the same reasons.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 8/26/2025 have been fully considered but they are not persuasive. Applicant argues in substance:
In other words, the difference between the cracked mode and the non-cracked mode is that parallel load operations are executed across different processing cycles in the cracked mode, rather than any changes to the load operations themselves.
This argument is not persuasive. First, Examiner notes that claim 1 does not expressly require “changes” to the load operations but rather requires the load instructions are replaced. It’s not until later claims (e.g., claim 12) that any changes are expressly noted and required. Under BRI the differences in the cracked and non-cracked mode meet the claim limitation as required. Secondly, Raja notes that in the cracked mode there are plural instructions whereas in the non-cracked mode there is a single instruction carrying out the same loads, thus the instructions [operations] are different.
For reasons that should be appreciated from the foregoing, Raja does not disclose: "a fused load instruction sequence for the plurality of registers that includes a load instruction for loading from multiple memory locations and an operation applied to a destination register of the fused load instruction," and "the operation is converted into a no-operation instruction," recited in independent claim 12.
This argument is not persuasive. Raja meets the register limitation for the reasons noted above. With regard to the no-op instruction, Examiner relied on Fulton for this aspect of the invention as noted in the Non-Final rejection of claim 13, which has now been incorporated into the rejection of amended claim 12.
In the interest of compact prosecution, Examiner suggests Applicant incorporate the allowable subject matter from claim 17 into claims 1 and 12 and cancel claim 21 to place the claims in condition for allowance. Should Applicant disagree with the above rejections/response to arguments then Examiner suggests Applicant clarify the destination register aspect of claims 1 and 12 to distinguish over loads as described in Raja. Examiner is available for an interview at examiner’s convenience to discuss potential amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William B Partridge whose telephone number is (571) 270-1402. The examiner can normally be reached Mon-Fri Noon-3 Pacific.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Fristoe can be reached at (571) 272-4926. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/William B Partridge/Supervisory Patent Examiner
Art Unit 2812
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