Prosecution Insights
Last updated: April 19, 2026
Application No. 18/622,340

PACKET SYNCHRONIZATION

Non-Final OA §102§103
Filed
Mar 29, 2024
Examiner
KIDANE, MEHERET WOLDEGEBREAL
Art Unit
2464
Tech Center
2400 — Computer Networks
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
13 granted / 15 resolved
+28.7% vs TC avg
Strong +20% interview lift
Without
With
+20.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
35 currently pending
Career history
50
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
63.2%
+23.2% vs TC avg
§102
34.7%
-5.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 15 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lei (US 20250386312). Regarding claim 1, Lei teaches an apparatus for wireless communication at a first user equipment (UE), comprising: one or more memories; and one or more processors, coupled to the one or more memories, individually or collectively configured to cause the first UE to (Paragraphs [0009]; [0037]; [0131] describes terminal device includes one or more processors and a memory causing the electronic device to implement the method): transmit a first packet to a network entity at a transmit time (Paragraphs [0033]; [0041]-[0042]; [0075]-[0076] describes the UE transmitting a data packet (first packet) to a network entity while recording a transmit timestamp T1 (transmit time)); and transmit a second packet, associated with the first packet, to a second UE with a timestamp that indicates the transmit time of the first packet (Paragraphs [0060]-[0061]; [0043]; [0047]; [0069] describes that the data packet forwarded to the destination device carries the first timestamp T1 (the transmit time of the original packet) the forwarded packet includes T1 embedded within it, and the time information transmitted separately (T2-T1 or T2) is derived from and directly references T1). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2, 3, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lei in view of Norman (US 7796601). Regarding claim 2, Lei doesn’t teach wherein the one or more processors are individually or collectively configured to cause the first UE to receive, from the second UE, assistance information for a suggested link mapping for the first packet and the second packet that is based at least in part on a congestion delay status on a link between the second UE and the network entity. However, in analogous art Norman teaches wherein the one or more processors are individually or collectively configured to cause the first UE to receive, from the second UE, assistance information for a suggested link mapping for the first packet and the second packet that is based at least in part on a congestion delay status on a link between the second UE and the network entity (Page 13, Col. 4, lines 60-65 Page 14, Col. 5, lines 7-16 describes the two path routing exists precisely to handle congestion. Routing first and second packet flows over diverse paths is to avoid congestion on any single link between the relay nodes and the destination ). Therefore, it would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lei to incorporate the teachings of Norman the first UE to proactively adjust its packet transmission behavior, such as delaying, dropping, or switching the path of a packet based on the second UE's feedback about network side congestion. Doing so solves the problem of single-path fragility in IP networks (Norman, Col. 1, lines 64 and Col. 2, lines 1-6). Regarding claim 3, Lei in view of Norman Lei teaches wherein to transmit the second packet, the one or more processors are individually or collectively configured to cause the first UE to transmit the second packet based at least in part on the assistance information (Paragraphs [0033]; [0043]; [0065]; [0089]-[0093] describes the UE could not transmit the second packet with the correct timestamp values without first receiving T5-T4 (assistance information). The transmission of the second packet is therefore based at least in part on the assistance information T5-T4). Claims 11 and 18 are rejected for the same reason as set forth in claim 2 respectively. Claim(s) 4-5, 8-10, 12 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lei in view of Liu (US 8488584). Regarding claim 4, Lei doesn’t teach wherein the one or more processors are individually or collectively configured to cause the first UE to transmit an indication of a synchronization duration during which the second UE is to forward the second packet after the transmit time. However, in analogous art Liu teaches wherein the one or more processors are individually or collectively configured to cause the first UE to transmit an indication of a synchronization duration during which the second UE is to forward the second packet after the transmit time (Page 12, Col. 3 lines 23-32, Page 12 Col. 4, lines 25-40 describes the first UE transmits a beacon/synchronization signal that contains a reserved bit set to “1.” This reserved bit is an explicit indication embedded in the signal that tells the receiving node both that a broadcast packet is coming and defines the window during which it will arrive). Therefore, it would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lei to incorporate the teachings of Liu an indication specifying a synchronization duration for forwarding the second packet after the transmit time to improve collisions and excessively long delayed time (Liu, Col. 5, lines 48-51). Regarding claim 5, Lei in view of Liu, Liu teaches wherein the one or more processors are individually or collectively configured to cause the first UE to transmit an indication of a synchronization duration during which a network entity is to receive the first packet (Page 12, Col. 3 lines 23-32, Page 12 Col. 4, lines 25-40 describes synchronization signal transmitted by the parent node (first UE) defines the active period, the window during which all packet transmission occur, including uplink point-to-point transmissions from the child node to the parent node. The beacon therefore constitutes a transmitted indication of a synchronization duration during which the network entity (Parent node) is to receive the first packet). Regarding claim 8, Lei teaches an apparatus for wireless communication at a second user equipment (UE), comprising: one or more memories; and one or more processors, coupled to the one or more memories, individually or collectively configured to cause the second UE to: receive (Paragraphs [0007]-[0009]; [0060] apparatus with one or more processors coupled to one or more memories), from a first UE, a second packet with a timestamp that indicates a transmit time of a first packet that is associated with the second packet (Paragraphs [0043]; [0047]; [0060]-[0061]; [0069] describes that the data packet forwarded to the destination device carries the first timestamp T1 (the transmit time of the original packet) the forwarded packet includes T1 embedded within it, and the time information transmitted separately (T2-T1 or T2) is derived from and directly references T1); Lei doesn’t teach and forward the second packet to a network entity within a synchronization duration after the transmit time of the first packet. However, in analogous art Liu teaches and forward the second packet to a network entity within a synchronization duration after the transmit time of the first packet (Page 12, Col. 4 lines 29-40 describes the communication device (second UE) receives a packet form the parent node and then forwards it to its child node (network entity) within a defined time window or within a period tied to the synchronization signal timing). Regarding claim 9, Lei in view of Liu, Liu teaches wherein the one or more processors are individually or collectively configured to cause the second UE to select a logical channel for the forwarding of the second packet based at least in part on one or more of the timestamp, the synchronization duration, or a remaining delay budget (Page 12, Col. 3, lines 34-41 describes the communication device uses timing information specifically whether the current time falls within the active period defined by the beacon timestamp to determine which transmission channel to use. If within the active period, the broadcast channel is selected. If outside the active period, no transmission occurs). Regarding claim 10, Lei in view of Liu, Liu teaches wherein the one or more processors are individually or collectively configured to cause the second UE to select a logical channel for the forwarding of the second packet based at least in part on a priority of the logical channel (Pages, 12 Col. 3, lines 44-53 describes a priority hierarchy between logical channels. Broadcasting is the preferred/higher priority channel for downlink forwarding to child nodes, while point-to-point is the preferred/higher priority channel for uplink transmission to parent nodes). Claim 12 is rejected for the same reason as set forth in claim 4 respectively. Claim 15 is rejected for the same reason as set forth in claim 8 respectively. Claim 16 is rejected for the same reason as set forth in claim 9 respectively. Claim 17 is rejected for the same reason as set forth in claim 10 respectively. Claim(s) 6-7, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lei in view of Bhalla et al. (US 2019/0045304). Regarding claim 6, Lei doesn’t teach wherein the one or more processors are individually or collectively configured to cause the first UE to receive a transmission status report for the second packet. However, in analogous art Bhalla teaches wherein the one or more processors are individually or collectively configured to cause the first UE to receive a transmission status report for the second packet (Paragraphs [0048]-[0049] describes the master controller receives or monitors for a transmission status report (ACK) specifically associated with a particular data packet (the second packet transmitted to slave device 106) the system tracks the transmission status on a per-packet basis). Therefore, it would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lei to incorporate the teachings of Bhalla the use of a presentation timestamp (PTS) or application timestamp (ATS) as the central synchronization mechanism. Slave devices use this timestamp to determine exactly when to play the audio, regardless of their individual processing delays (Bhalla, Paragraph [0021]). Regarding claim 7, Lei doesn’t teach wherein the one or more processors are individually or collectively configured to cause the first UE to set the timestamp to a default value based at least in part on the first UE transmitting the second packet before the first packet. However, in analogous art Bhalla teaches wherein the one or more processors are individually or collectively configured to cause the first UE to set the timestamp to a default value based at least in part on the first UE transmitting the second packet before the first packet (Paragraphs [0042]; [0048]-[0049]; [0059] describes the timestamps are assigned at first transmission and remain fixed thereafter. When packet is retransmitted, the timestamp doesn’t change, it remains at its original value, which functions as the default value. The ordering of T0, T2, T8, T10 also shows that timestamp values are pre-assigned and not recalculated on retransmission). Claims 13 and 19 are rejected for the same reason as set forth in claim 6 respectively. Claim(s) 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lei in view of Norman in further view of Bhalla. Regarding claim 14, Lei in view of Norman don’t teach wherein the one or more processors are individually or collectively configured to cause the second UE to delay the forwarding of the second packet based at least in part on the timestamp indicating a default value. In analogous art Bhalla teaches wherein the one or more processors are individually or collectively configured to cause the second UE to delay the forwarding of the second packet based at least in part on the timestamp indicating a default value (Paragraphs [0038]; [0048]-[0049];[0053]; [0059] describes that the slave device (second UE) delays the forwarding/output of a data packet based on the timestamp value. The slave host 206 actively waits, delays forwarding until the timer reaches the value defined by the sum of the time timestamp and the presentation delay ). Therefore, it would have been to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lei and Norman to incorporate the teachings of Bhalla the use of a presentation timestamp (PTS) or application timestamp (ATS) as the central synchronization mechanism. Slave devices use this timestamp to determine exactly when to play the audio, regardless of their individual processing delays (Bhalla, Paragraph [0021]). Claim 20 is rejected for the same reason as set forth in claim 14 respectively. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEHERET WOLDEGEBREAL KIDANE whose telephone number is (571)270-3642. The examiner can normally be reached M-F8:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ricky Ngo can be reached at 571-272-3139. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Chandrahas B Patel/Primary Examiner, Art Unit 2464 /M.W.K./ Examiner, Art Unit 2464
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Prosecution Timeline

Mar 29, 2024
Application Filed
Mar 10, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+20.0%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 15 resolved cases by this examiner. Grant probability derived from career allow rate.

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