DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The use of the terms LTE® (Paragraph 3, line 1, and Paragraph 52, line 2), Wi-Fi® (Paragraph 52, line 1), WiMAX® (Paragraph 52, line 2), and Bluetooth® (Paragraph 52, line 8), which are trade names or marks used in commerce, has been noted in this application. The terms should be accompanied by the generic terminology; furthermore the terms should be capitalized wherever they appear or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the terms.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
The disclosure is objected to because of the following informalities: On Paragraph 13, lines 6 and 8, and Paragraph 22, lines 6 and 8, replace “charge pimping” with “charge pumping”.
Appropriate correction is required.
Claim Objections
Claims 5-6 and 10-16 are objected to because of the following informalities:
On claim 5, lines 7 and 10-11, and claim 15, lines 7 and 10-11, replace “charge pimping” with “charge pumping”. Claim 6 is likewise objected to under this logic by virtue of its dependency on claim 5.
On claim 10, lines 4-5, replace “either one or both power supply voltage” with “either one or both power supply voltages”. Claims 11-16 are likewise objected to under this logic by virtue of their dependency on claim 10.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the low level" in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the low level of the first logic signal and the low level of the second logic signal” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 9-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gao et al. (Patent Publication Number WO 2025/060799 A1), hereafter referred to as Gao.
Regarding claim 1, Gao discloses:
A power selection switch circuit (Gao, Fig. 11) configured to select either one or both of a first power supply voltage (Fig. 11, Vcc-1) and a second power supply voltage (Fig. 1, Vcc-n), and supply the selected power supply voltage to a power amplifier (Fig. 11, see connection between Vcc-1, Vcc-n, and PA), the power selection switch circuit comprising: an n-type first transistor (Fig. 11, see element 10 coupled to Vcc-1, consider detail shown in Fig. 1, and transistor 101) configured to turn on in response to a first switching control signal having a first voltage (Page 7, Paragraph 3, lines 5-8) generated by charge pumping the first power supply voltage (Page 14, Paragraph 4, line 1), and supply the first power supply voltage to a power supply terminal of the power amplifier when turned on (Fig. 11, see connection between 10 coupled to Vcc-1 and PA); and an n-type second transistor (Fig. 11, see element 10 coupled to Vcc-n, consider detail shown in Fig. 1, and transistor 101) configured to turn on in response to a second switching control signal having a second voltage (Page 7, Paragraph 3, lines 5-8) generated by charge pumping the second power supply voltage (Page 14, Paragraph 4, line 1), and supply the second power supply voltage to the power supply terminal of the power amplifier when turned on (Fig. 11, see connection between 10 coupled to Vcc-n and PA).
Regarding claim 9, Gao further discloses:
A power amplifier module (Gao, Fig. 11), comprising: the power amplifier (Fig. 11, PA) and the power selection switch circuit of claim 1 (Fig. 11, 90).
Regarding claim 10, Gao discloses:
A power amplifier module (Gao, Fig. 11) comprising: a power amplifier (Fig. 11, see PA) configured to receive a power supply voltage from a power supply terminal (Fig. 11, see connection between power ICs 10 and PA), and amplify an input signal (Fig. 11, see input of PA) and output the amplified signal (Fig. 11, see output of PA); and a power selection switch circuit (Fig. 11, 90) configured to provide either one or both power supply voltage of a first power supply voltage (Fig. 11, Vcc-1), supplied from a first power integrated circuit (IC) (Fig. 11, see Vcc-1 and instance of 10 coupled to it), and a second power supply voltage (Fig. 11, Vcc-n), supplied from a second power IC (Fig. 11, see Vcc-N and instance of 10 coupled to it) to the power supply terminal (Fig. 11, see connection between 10 and PA), wherein the power selection switch circuit comprises: an n-type first transistor (Fig. 11, see element 10 coupled to Vcc-1, consider detail shown in Fig. 1, and transistor 101) configured to have a first terminal connected to the first power IC (Fig. 11, see connection between 10 and Vcc-1), a second terminal connected to the power supply terminal (Fig. 11, see connection between 10 coupled to Vcc-1 and PA), and a control terminal (Fig. 1, consider gate of transistor 101) receiving a first switching control signal having a first voltage (Page 7, Paragraph 3, lines 5-8) generated by charge pumping the first power supply voltage (Page 14, Paragraph 4, line 1); and an n-type second transistor (Fig. 11, see element 10 coupled to Vcc-n, consider detail shown in Fig. 1, and transistor 101) configured to have a first terminal connected to the second power IC (Fig. 11, see connection between 10 and Vcc-n), a second terminal connected to the power supply terminal (Fig. 11, see connection between 10 coupled to Vcc-n and PA), and a control terminal (Fig. 1, consider gate of transistor 101) receiving a second switching control signal having a second voltage (Page 7, Paragraph 3, lines 5-8) generated by charge pumping the second power supply voltage (Page 14, Paragraph 4, line 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Gao as applied to claims 1 and 10, respectively, above, and further in view of Miwa et al. (Patent Number US 11,009,902 B1), as cited by applicant, hereafter referred to as Miwa.
Regarding claim 2, Gao fails to disclose:
further comprising: a switching controller configured to generate the first switching control signal and the second switching control signal using a first bit signal and a second bit signal externally input so that a transistor that is turned on from a turn-off state, among the n-type first transistor and the n-type second transistor, is turned on after being delayed by a predetermined time, and a transistor that is turned off from a turn-on state, among the n-type first transistor and the n-type second transistor, is turned off immediately, wherein the n-type first transistor is configured to turn off in response to the first switching control signal having a third voltage lower than the first voltage, and the second transistor is configured to turn off in response to the second switching control signal having a fourth voltage lower than the second voltage.
However, Miwa teaches further comprising: a switching controller (Miwa, Fig. 2, 40) configured to generate the first switching control signal (Fig. 2, MDV2HEN) and the second switching control signal (Fig. 2, MDV2LEN) using a first bit signal (Fig. 2, consider signal at input of 62) and a second bit signal externally input (Fig. 2, consider signal at input of 61) so that a transistor that is turned on from a turn-off state, among the n-type first transistor and the n-type second transistor, is turned on after being delayed by a predetermined time (Col. 4, lines 46-47), and a transistor that is turned off from a turn-on state, among the n-type first transistor and the n-type second transistor, is turned off immediately (Col. 4, lines 46-48), wherein the n-type first transistor is configured to turn off in response to the first switching control signal having a third voltage lower than the first voltage (Col. 4, lines 35-39), and the second transistor is configured to turn off in response to the second switching control signal having a fourth voltage lower than the second voltage (Col. 4, lines 26-30).
Gao and Miwa are both considered to be analogous to the claimed invention because they are in the same field of improving power supply selection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Miwa to include the switching controller of Miwa in the circuit of Gao, which would have the effect of preventing erroneous switch activation in the circuit of Gao (Miwa, Col. 4, lines 51-54).
Regarding claim 3, Gao fails to disclose:
wherein the switching controller comprises: a logic circuit configured to generate a first logic signal for generating the first switching control signal and a second logic signal for generating the second switching control signal by combining the first bit signal and the second bit signal; a first delay circuit configured to delay the first logic signal to generate a first delay signal; a second delay circuit configured to delay the second logic signal to generate a second delay signal; a first buffer control circuit configured to supply the first voltage or the third voltage as the first switching control signal to a control terminal of the n-type first transistor in response to the first delay signal; and a second buffer control circuit configured to supply the second voltage or the fourth voltage as the second switching control signal to a control terminal of the n-type second transistor in response to the second delay signal.
However, Miwa further teaches wherein the switching controller comprises: a logic circuit (Miwa, Fig. 2, 61 and 62) configured to generate a first logic signal for generating the first switching control signal (Fig. 2, see output of 62) and a second logic signal for generating the second switching control signal (Fig. 2, see output of 61) by combining the first bit signal and the second bit signal (Fig. 2, consider inputs of 61 and 62); a first delay circuit (Fig. 2, 62) configured to delay the first logic signal to generate a first delay signal (Col. 4, lines 46-48); a second delay circuit (Fig. 2, 61) configured to delay the second logic signal to generate a second delay signal (Col. 4, lines 46-48); a first buffer control circuit (Fig. 2, 52) configured to supply the first voltage or the third voltage as the first switching control signal to a control terminal of the n-type first transistor in response to the first delay signal (Fig. 2, see connection between 52 and gate of 42); and a second buffer control circuit (Fig. 2, 51) configured to supply the second voltage or the fourth voltage as the second switching control signal to a control terminal of the n-type second transistor in response to the second delay signal (Fig. 2, see connection between 51 and gate of 41).
Gao and Miwa are both considered to be analogous to the claimed invention because they are in the same field of improving power supply selection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Miwa to include the switching controller of Miwa in the circuit of Gao, which would have the effect of preventing erroneous switch activation in the circuit of Gao (Miwa, Col. 4, lines 51-54).
Regarding claim 4, Gao fails to disclose:
wherein the first bit signal and the second bit signal have a value of 0 or 1, and the logic circuit is configured to set both the first logic signal and the second logic signal to a low level so that when the first bit signal and the second bit signal are both 1 or both 0, both the n-type first transistor and the n-type second transistor are turned off.
However, Miwa further teaches wherein the first bit signal and the second bit signal have a value of 0 or 1, and the logic circuit is configured to set both the first logic signal and the second logic signal to a low level so that when the first bit signal and the second bit signal are both 1 or both 0, both the n-type first transistor and the n-type second transistor are turned off (Miwa, Col. 4, lines 22-39).
Gao and Miwa are both considered to be analogous to the claimed invention because they are in the same field of improving power supply selection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Miwa to include the switching controller of Miwa in the circuit of Gao, which would have the effect of preventing erroneous switch activation in the circuit of Gao (Miwa, Col. 4, lines 51-54).
Regarding claim 5, Gao further discloses:
wherein the switching controller further comprises: a first clock generator (Gao, Fig. 9, ClkA and ClkB) configured to operate in response to the first logic signal (Page 14, Paragraph 8, lines 1-3), and generate a first clock signal having a fifth voltage and a sixth voltage lower than the fifth voltage (Page 14, Paragraph 7, lines 1-8); a second clock generator (Gao, Fig. 9, ClkA and ClkB) configured to operate in response to the second logic signal (Page 14, Paragraph 8, lines 1-3), and generate a second clock signal having the fifth voltage and the sixth voltage (Page 14, Paragraph 7, lines 1-8); a first charge pump circuit (see transistors of Fig. 9) configured to generate the first voltage by charge pimping the first power supply voltage by the fifth voltage in response to the first clock signal (Page 14, Paragraph 7, lines 1-5), and provide the first voltage to the first buffer control circuit (Fig. 9, see Vout_1); and a second charge pump circuit (see transistors of Fig. 9) configured to generate the second voltage by charge pimping the second power supply voltage by the fifth voltage in response to the second clock signal (Page 14, Paragraph 7, lines 1-5), and provide the second voltage to the second buffer control circuit (Fig. 9, see Vout_1).
Regarding claim 6, Gao further discloses:
wherein the first logic signal and the second logic signal have a high level and a low level (Gao, Page 14, Paragraph 7, lines 1-5), and the first clock generator and the second clock generator operate at the high level of the first logic signal and the high level of the second logic signal, and do not operate at the low level (Page 14, Paragraph 7, lines 1-8).
Regarding claim 11, Gao fails to disclose:
wherein the power selection switch circuit further comprises a switching controller configured to generate the first switching control signal and the second switching control signal so that the n-type first transistor and the n-type second transistor are turned on after being delayed by a predetermined time when the n-type first transistor and the n-type second transistor change from the turn-off state to the turn-on state.
However, Miwa teaches wherein the power selection switch circuit further comprises a switching controller (Miwa, Fig. 2, 40) configured to generate the first switching control signal (Fig. 2, MDV2HEN) and the second switching control signal (Fig. 2, MDV2LEN) so that the n-type first transistor and the n-type second transistor are turned on after being delayed by a predetermined time when the n-type first transistor and the n-type second transistor change from the turn-off state to the turn-on state (Col. 4, lines 46-47).
Gao and Miwa are both considered to be analogous to the claimed invention because they are in the same field of improving power supply selection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Miwa to include the switching controller of Miwa in the circuit of Gao, which would have the effect of preventing erroneous switch activation in the circuit of Gao (Miwa, Col. 4, lines 51-54).
Regarding claim 12, Gao fails to disclose:
wherein the n-type first transistor is configured to turn off in response to the first switching control signal having a third voltage lower than the first voltage, and the n-type second transistor is configured to turn off in response to the second switching control signal having a fourth voltage lower than the second voltage.
However, Miwa further teaches wherein the n-type first transistor is configured to turn off in response to the first switching control signal having a third voltage lower than the first voltage (Miwa, Col. 4, lines 35-39), and the n-type second transistor is configured to turn off in response to the second switching control signal having a fourth voltage lower than the second voltage (Col. 4, lines 26-30).
Gao and Miwa are both considered to be analogous to the claimed invention because they are in the same field of improving power supply selection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Miwa to include the switching controller of Miwa in the circuit of Gao, which would have the effect of preventing erroneous switch activation in the circuit of Gao (Miwa, Col. 4, lines 51-54).
Regarding claim 13, Gao fails to disclose:
wherein the switching controller comprises: a logic circuit configured to generate a first logic signal for generating the first switching control signal and a second logic signal for generating the second switching control signal by combining a first bit signal and a second bit signal input from an outside; a first delay circuit configured to delay the first logic signal to generate a first delay signal; a second delay circuit configured to delay the second logic signal to generate a second delay signal; a first buffer control circuit configured to supply the first voltage or the third voltage as the first switching control signal to a control terminal of the n-type first transistor in response to the first delay signal; and a second buffer control circuit configured to supply the second voltage or the fourth voltage as the second switching control signal to a control terminal of the n-type second transistor in response to the second delay signal.
However, Miwa further teaches wherein the switching controller comprises: a logic circuit (Miwa, Fig. 2, 61 and 62) configured to generate a first logic signal for generating the first switching control signal (Fig. 2, see output of 62) and a second logic signal for generating the second switching control signal (Fig. 2, see output of 61) by combining a first bit signal and a second bit signal input from an outside (Fig. 2, consider inputs of 61 and 62); a first delay circuit (Fig. 2, 62) configured to delay the first logic signal to generate a first delay signal (Col. 4, lines 46-48); a second delay circuit (Fig. 2, 61) configured to delay the second logic signal to generate a second delay signal (Col. 4, lines 46-48); a first buffer control circuit (Fig. 2, 52) configured to supply the first voltage or the third voltage as the first switching control signal to a control terminal of the n-type first transistor in response to the first delay signal (Fig. 2, see connection between 52 and gate of 42); and a second buffer control circuit (Fig. 2, 51) configured to supply the second voltage or the fourth voltage as the second switching control signal to a control terminal of the n-type second transistor in response to the second delay signal (Fig. 2, see connection between 51 and gate of 41).
Gao and Miwa are both considered to be analogous to the claimed invention because they are in the same field of improving power supply selection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Miwa to include the switching controller of Miwa in the circuit of Gao, which would have the effect of preventing erroneous switch activation in the circuit of Gao (Miwa, Col. 4, lines 51-54).
Regarding claim 14, Gao fails to disclose:
wherein the first bit signal and the second bit signal have a value of 0 or 1, and the logic circuit is configured to set both the first logic signal and the second logic signal to a low level so that when the first bit signal and the second bit signal are both 1 or both 0, both the n-type first transistor and the n-type second transistor are turned off.
However, Miwa further teaches wherein the first bit signal and the second bit signal have a value of 0 or 1, and the logic circuit is configured to set both the first logic signal and the second logic signal to a low level so that when the first bit signal and the second bit signal are both 1 or both 0, both the n-type first transistor and the n-type second transistor are turned off (Miwa, Col. 4, lines 22-39).
Gao and Miwa are both considered to be analogous to the claimed invention because they are in the same field of improving power supply selection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Miwa to include the switching controller of Miwa in the circuit of Gao, which would have the effect of preventing erroneous switch activation in the circuit of Gao (Miwa, Col. 4, lines 51-54).
Regarding claim 15, Gao further discloses:
wherein the switching controller comprises: a first clock generator (Gao, Fig. 9, ClkA and ClkB) configured to operate in response to the first logic signal (Page 14, Paragraph 8, lines 1-3) and generate a first clock signal having a fifth voltage and a sixth voltage lower than the fifth voltage (Page 14, Paragraph 7, lines 1-8); a second clock generator (Gao, Fig. 9, ClkA and ClkB) configured to operate in response to the second logic signal (Page 14, Paragraph 8, lines 1-3) and generate a second clock signal having the fifth voltage and the sixth voltage (Page 14, Paragraph 7, lines 1-8); a first charge pump circuit (see transistors of Fig. 9) configured to generate the first voltage by charge pimping the first power supply voltage by the fifth voltage in response to the first clock signal (Page 14, Paragraph 7, lines 1-5), and provide the first voltage to the first buffer control circuit (Fig. 9, see Vout_1); and a second charge pump circuit (see transistors of Fig. 9) configured to generate the second voltage by charge pimping the second power supply voltage by the fifth voltage in response to the second clock signal (Page 14, Paragraph 7, lines 1-5), and provide the second voltage to the second buffer control circuit (Fig. 9, see Vout_1).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gao in view of Miwa as applied to claim 4 above, and further in view of Tae-Hee et al. (Patent Number JP 4,566,369 B2), hereafter referred to as Tae-Hee.
Regarding claim 7, Gao and Miwa fail to disclose:
wherein the logic circuit comprises: a NAND gate configured to receive the first bit signal and the second bit signal; a first AND gate configured to receive the first bit signal and an output of the NAND gate, and output the first logic signal; and a second AND gate configured to receive the second bit signal and an output of the NAND gate, and output the second logic signal.
However, Tae-Hee teaches wherein the logic circuit comprises: a NAND gate (Tae-Hee, Fig. 14, 526) configured to receive the first bit signal (Fig. 14, INT_S1KPGM) and the second bit signal (Fig. 14, PGM_FLPMAX); a first AND gate (Fig. 14, 528) configured to receive the first bit signal and an output of the NAND gate (Fig. 14, consider that 528 receives data about INT_S1KPGM via 526), and output the first logic signal (Fig. 14, consider output of 528); and a second AND gate (Fig. 14, 529) configured to receive the second bit signal and an output of the NAND gate (Fig. 14, consider that 529 receives data about PGM_FLPMAX via 526), and output the second logic signal (Fig. 14, consider output of 529).
Gao, Miwa, and Tae-Hee are all considered to be analogous to the claimed invention because they are in the same field of improving power supply selection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Tae-Hee to include the logic circuit of Tae-Hee in the circuit of Gao, which would have the effect of accurately checking fail states of the circuit devices of Gao (Tae-Hee, Paragraph 79, lines 1-6).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Gao in view of Miwa as applied to claim 3 above, and further in view of Henzler et al. (Patent Publication Number US 2021/0075372 A1), hereafter referred to as Henzler.
Regarding claim 8, Gao fails to disclose:
wherein the first delay circuit comprises: a first delay cell configured to delay the first logic signal; and a first AND gate configured to receive the first logic signal and a signal delayed by the first delay cell, and wherein the second delay circuit comprises: a second delay cell configured to delay the second logic signal; and a second AND gate configured to receive the second logic signal and a signal delayed by the second delay cell.
However, Miwa further teaches wherein the first delay circuit comprises: a first delay cell (Miwa, Fig. 2, 62) configured to delay the first logic signal (Fig. 2, consider input of 62); and wherein the second delay circuit comprises: a second delay cell (Fig. 2, 61) configured to delay the second logic signal (Fig. 2, consider input of 61); but fails to teach and a first AND gate configured to receive the first logic signal and a signal delayed by the first delay cell, and a second AND gate configured to receive the second logic signal and a signal delayed by the second delay cell.
However, Henzler teaches and a first AND gate (Henzler, Fig. 7, 796) configured to receive the first logic signal (Fig. 7, see left side input of 796) and a signal delayed by the first delay cell (Fig. 7, see connection between right side input of 796 and delay cell 795), and a second AND gate (Fig. 7, 796) configured to receive the second logic signal (Fig. 7, see left side input of 796) and a signal delayed by the second delay cell (Fig. 7, see connection between right side input of 796 and delay cell 795).
Gao, Miwa, and Henzler are all considered to be analogous to the claimed invention because they are in the same field of improving power supply selection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Miwa and Henzler to include the switching controller of Miwa in the circuit of Gao, which would have the effect of preventing erroneous switch activation in the circuit of Gao (Miwa, Col. 4, lines 51-54), and to include the AND gate of Henzler in the circuit of Gao, which would have the effect of suppressing undesirable signal distortions (Henzler, Paragraph 56, lines 8-13).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Gao as applied to claim 10 above, and further in view of Sasaki et al. (Patent Publication Number US 2020/0091874 A1), hereafter referred to as Sasaki.
Regarding claim 16, Gao fails to disclose:
wherein the n-type first transistor comprises a plurality of third transistors connected in parallel, the n-type second transistor comprises a plurality of fourth transistors connected in parallel, and the plurality of third transistor and the plurality of fourth transistor are n-type transistors.
However, Sasaki teaches wherein the n-type first transistor comprises a plurality of third transistors connected in parallel (Sasaki, Fig. 2, see plurality of transistors Q1 in parallel), the n-type second transistor comprises a plurality of fourth transistors connected in parallel (Fig. 2, see plurality of transistors Q1 in parallel), and the plurality of third transistor and the plurality of fourth transistor are n-type transistors (Fig. 2, see that Q1 is an n-type transistor).
Gao and Sasaki are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifier circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Gao to incorporate the teachings of Gao to include the plurality of parallel transistors of Sasaki in the circuit of Gao, which would have the effect of reducing the size of the circuit elements of Gao.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Delano et al. (Patent Number US 7,733,178 B1) discloses (Fig. 3) an amplifier circuit with a charge pumping power supply selection circuit.
Cahill et al. (Patent Publication Number US 2025/0023520 A1) discloses (Fig. 13) a power amplifier circuit with a power supply selection circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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