DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 03/29/2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
“BJ joint” reads as “butt joint joint” (0006, 0011, 0016, 0019, 0024-0036, at least).
Appropriate correction is required.
Claim Interpretation
First/second-conductivity type (with hyphen) different from first/second conductivity type (without hyphen)
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 (and 14 via dependency) rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 indefinite due to “a butt joint” lines 8-9, “an end portion” lines 17-18, “a position” line 20. These elements already recited in independent claim 1. It is unclear if the claim 8 references are new elements or references to existing elements from claim 1. Examiner interprets them to be new elements specific to the second BJ joint region, second electrode, second voltage applying end, etc. Applicant is advised to further distinguish between these new claim 8 butt joint, end portion, and position elements and the previous ones from claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-13 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Wakayama (JP-2014082411-A, machine translation “Wakayama_English” cited and included herewith).
Regarding claim 1, Wakayama discloses a semiconductor integrated optical device (fig. 2 + annotated fig. 2, 0032), comprising: a substrate (substrate 101, 0047); a first core layer placed so as to extend in a predetermined direction on the substrate (first core layer 102+103+104 extends left to right in fig. 2 on 101, 0047-0048); a second core layer placed on the substrate so as to extend in the predetermined direction and so as to be side by side with the first core layer in the predetermined direction (second core layer 110 on 101 and extending left to right and side by side with 102+103+104, 0049); a second-conductivity type semiconductor layer placed on the first core layer and the second core layer (second conductivity type p semiconductor layer 112+113 on 102+103+104 and 110); a first electrode placed on the second-conductivity type semiconductor layer so as to overlap with at least the first core layer (first electrode 114 on 112+113 and overlapping with 102+103+104, 0069); and a protrusion portion of a first conductivity type which protrudes from the substrate toward the first electrode (protrusion portion 109 first conductivity type n and protrudes from 101 toward 114, 0049-0050), and which is located between the first core layer and the second core layer to join the first core layer and the second core layer to each other by a butt joint (109 between 102+103+104 and 110 and joins them by a butt joint, 0003-0004), the semiconductor integrated optical device further comprising, in plan view: a BJ joint region in which the protrusion portion is formed (annotated fig. 2 BJR); a first optical function device region which is adjacent to the BJ joint region in the predetermined direction (FR adjacent to BJR left to right), and in which the first core layer and at least a part of the first electrode are located (102+103+104 and 114 in FR); and a second optical function device region which is adjacent to the BJ joint region on a side opposite from the first optical function device region (SR adjacent to BJR opposite FR), and in which the second core layer is located (110 in SR), wherein the first electrode has a voltage applying end in an end portion on the BJ joint region side on a surface that is in contact with the second-conductivity type semiconductor layer (114 has voltage applying end VAE in end portion (right half of 114) on BJR side on (bottom) surface that is in physical + electrical contact with 112+113), and wherein the voltage applying end is placed at a position apart from the BJ joint region in the first optical function device region (VAE placed at a position apart from BJR in the FR).
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Annotated fig. 2 (CLAIM 1)
Regarding claim 2, Wakayama discloses the semiconductor integrated optical device according to claim 1, wherein the protrusion portion has a side portion end which is in contact with the first core layer in a sectional view and which is closest in position to the first core layer side (109 has SPE (left surface of 109) in physical contact with 102+103+104), and wherein, when a line that runs along a normal line direction of the substrate through the side portion end is defined as a first virtual line (first virtual line FVL runs normal to top surface of 101 through SPE), a line that runs through the side end portion and the voltage applying end closest to the substrate in a sectional view is defined as a second virtual line (second virtual line SVL runs through SPE and VAE closest to 101), and an angle formed by the first virtual line and the second virtual line is represented by θ, the angle θ is 30° or more and 60° or less (clearly, there exists FVL + SVL pair with angle between 30 and 60 degrees).
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Annotated fig. 2 (claims 2+3)
Regarding claim 3, Wakayama discloses the semiconductor integrated optical device according to claim 2, wherein the angle θ is 45° or more (FVL + SVL can make angle 45 to 60 degrees).
Regarding claim 4, Wakayama discloses the semiconductor integrated optical device according to claim 1, wherein the first core layer includes an active layer (102+103+104 includes active layer 103, 0047), and wherein a front end of the protrusion portion in a normal line direction of the substrate is located above a top surface of the active layer (front end of 109 in NLD of 101 located above top surface of 103).
Regarding claim 5, Wakayama discloses the semiconductor integrated optical device according to claim 1, wherein the first core layer includes an optical confinement layer of a second conductivity type (102+103+104 includes optical confinement layer 104, 0047), and wherein a front end of the protrusion portion in a normal line direction of the substrate is in contact with the optical confinement layer (front end (left end) of 109 in NLD of 101 in physical contact with 104).
Regarding claim 6, Wakayama discloses the semiconductor integrated optical device according to claim 1, wherein the second-conductivity type semiconductor layer includes a contact layer of a second conductivity type (112+113 includes p-type contact layer 113, 0047), and wherein the voltage applying end is a contact point at which the first electrode and the contact layer of the second conductivity type are in contact with each other (VAE at contact point at which 114 and 113 are in physical contact with each other).
Regarding claim 7, Wakayama discloses the semiconductor integrated optical device according to claim 1, wherein the protrusion portion includes a side portion end which is in contact with the first core layer and which is closest in position to the first core layer side (109 includes SPE (left surface of 109 to left of BJR boundary) in contact with and closest in position to 102+103+104), and another side portion end which is in contact with the second core layer and which is closest in position to the second core layer side (109 includes ASPE (right surface of 109 to right of BJR boundary) in contact with and closest in position to 110), and wherein the BJ joint region is defined by a region sandwiched between the side portion end and the another side portion end (BJR sandwiched between SPE and ASPE).
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Annotated fig. 2 (claim 7)
Regarding claim 10, Wakayama discloses the semiconductor integrated optical device according to claim 1, wherein the substrate is a first-conductivity type semiconductor substrate (101 is first type n).
Regarding claim 11, Wakayama discloses the semiconductor integrated optical device according to claim 10, further comprising a counter electrode on a surface opposite from a surface of the substrate on which the first core layer is formed (counter electrode 115 on bottom surface of 101 opposite top 101 surface w/ 102+103+104, 0069).
Regarding claim 12, Wakayama discloses the semiconductor integrated optical device according to claim 1, wherein the first optical function device region functions as a semiconductor laser (FR functions as semiconductor laser, 0046-0047).
Regarding claim 13, Wakayama discloses the semiconductor integrated optical device according to claim 1, wherein the second optical function device region functions as a connecting waveguide (SR functions as connecting waveguide, 0046-0047).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakayama in view of Kim (US-20120281274-A1).
Regarding claim 8, Wakayama discloses the semiconductor integrated optical device according to claim 1, with BJ regions comprising protrusion portions of the first conductivity type which protrude from the substrate toward the electrodes (BJR contains 109 of first (n) type protruding from 101 toward 114).
Wakayama does not disclose further comprising: a third core layer placed on the substrate so as to extend in the predetermined direction and so as to be side by side with the second core layer in the predetermined direction; a second electrode placed on the second-conductivity type semiconductor layer so as to overlap with at least the third core layer; and a second protrusion portion of the first conductivity type which protrudes from the substrate toward the second electrode, and which is located between the second core layer and the third core layer to join the second core layer and the third core layer to each other by a butt joint, the semiconductor integrated optical device further comprising, in plan view: a second BJ joint region which is adjacent to the second optical function device region in the predetermined direction, and in which the second protrusion portion is formed; and a third optical function device region which is adjacent to the second BJ joint region on a side opposite from the second optical function device region, and in which the third core layer is located, wherein the second electrode includes a second voltage applying end at an end portion on the second BJ joint region side on a surface that is in contact with the second-conductivity type semiconductor layer, and wherein the second voltage applying end is provided at a position apart from the second BJ joint region in the third optical function device region.
Kim discloses an optical device with a third core layer placed on a substrate so as to extend in a predetermined direction and so as to be side by side with a second core layer in the predetermined direction (fig. 2 third core layer LMC extends left to right and side by side with second core layer MCC2, 0051-0053); a second electrode placed on a second-conductivity type semiconductor layer so as to overlap with at least the third core layer (second electrode LME on second type (p) layer 150 and overlaps LMC, 0064, 0074); and a BJ portion which is located between the second core layer and the third core layer to join the second core layer and the third core layer to each other by a butt joint (BJ portion BI3 between MCC2 and LMC to join them by butt joint, 0053), the semiconductor integrated optical device further comprising, in plan view: a second BJ joint region which is adjacent to the second optical function device region in the predetermined direction (BJ joint region (region sandwiching BI3 in plan view) adjacent to an equivalent second op func region in left to right direction, second region left of BI3 joint region); and a third optical function device region which is adjacent to the second BJ joint region on a side opposite from the second optical function device region (third optical function device region (to the right of BI3 region) opposite second region), and in which the third core layer is located (LMC located in third region to right of BI3), wherein the second electrode includes a second voltage applying end at an end portion on the second BJ joint region side on a surface that is in contact with the second-conductivity type semiconductor layer (LME includes second voltage applying end (bottom surface of LME) at end portion of BI3 region on a surface (bottom surface) that is in physical/electrical contact with 150), and wherein the second voltage applying end is provided at a position apart from the second BJ joint region in the third optical function device region (bottom surface of LME provided apart from BI3 region and located in region to right of BI3 (third OFD region)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the structures required by claim 8 and make the third optical region a modulator to allow for clean integration of signal modulation functionality (Kim 0004). Using same Wakayama butt joint between modulator and rest of device would simplify manufacturing process compared to one using additional type of joint.
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Kim fig. 3 w/ second BJ joint region (claim 8)
Regarding claim 14, modified Wakayama discloses the semiconductor integrated optical device according to claim 8, wherein the third optical function device region functions as a modulator (claim 8 modification and Kim 0051).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakayama in view of Nakamura (US-20200328575-A1).
Regarding claim 9, Wakayama discloses the semiconductor integrated optical device according to claim 1, wherein an insulating film is formed on cladding layer 112 (0069).
Wakayama does not disclose wherein a part of the first electrode is placed in the BJ joint region, and wherein, in the BJ joint region, an insulating film is placed between the first electrode and the second-conductivity type semiconductor layer.
Nakamura discloses an optical device with electrodes extending over a butt joint region between a laser region and a waveguide region (fig. 2 electrodes 104a-d cover junction between butt-joined 101 + 102 regions, 0025, 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to extend the first electrode 114 at least into the BJ joint region and over insulating film covering 112 to allow for greater positional freedom when attaching electrode to an external power source.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kitatani US-20080317422-A1.
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/A.E./Examiner, Art Unit 2828
/MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828
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