DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 19 June 2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Copies of the following references were not received:
TW I666545,
TW I599960,
U.S. Patent Application No. 17676668,
U.S. Patent Application No. 17676683,
U.S. Patent Application No. 17676665.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the budged amount assigned to at least one of the plurality of components” in lines 11-12. There is insufficient antecedent basis for this limitation in the claims. There is no prior original recitation of a budget amount assigned to at least one of the plurality of components per se. Claim 1 has previously established a budget amount assigned to a given component, but it is unclear whether this budgeted amount is the same amount as that assigned to the at least one of the plurality of components. Claim 1 is additionally indefinite because the last line recites “the budged amount assigned”. This recitation is ambiguous because claim 1 has previously established at least two budgeted amounts (the given component and the at least one of the plurality).
Claim 4 is rejected as being indefinite for the following language: “detecting whether or not the power control the power control applied by the power reduction signal exceeds the threshold”.
Claim 8 recites the limitation “at least one of the components” in line 1. This language is indefinite because it unclear whether this establishes a new set of components different from the “plurality of components” originally recited in claim 1. Claim 8 is additionally rejected as being indefinite because it recites the power reduction signal being provided to at least one of the CPUs (plural) in the last line. Claim 8 has previously established “one or more” CPUs. The broadest reasonable interpretation (BRI) of “one or more” includes embodiments with only one CPU, whereas the language in the last line assumes plural CPUs. Claim 8 is therefore indefinite because it is inconsistent with respect to the number of CPUs in the claim.
Claim 10 is rejected on similar grounds as claim 8 with respect to the number of CPUs. The BRI of “one or more” includes embodiments of one CPU or plural CPUs, while the subsequent language of “the CPU processors” assumes only plural CPUs.
Claim 12 recites the limitation “the power management unit coupled to the integrated circuit” in line 18. There is insufficient antecedent basis for this limitation in the claim. Claim 12 has previously established a power management unit in line 7, but has not clearly indicated that the power management unit is coupled to the integrated circuit.
Claim 19 is rejected on the same basis as claim 12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 6, and 8-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gendler et al., U.S. Patent Application Publication No. 2020/0333867.
Regarding claim 1, Gendler discloses an integrated circuit [Fig. 1: multicore processor 110] comprising:
a plurality of components [cores 115], wherein a given component of the plurality of components is configured to manage power consumption [para. 0028: “In response to receiving a signal 223 indicating that a measured current exceeds a throttling threshold, the receiving one of the PMAs 211 may determine whether to throttle the corresponding one of the cores 115.”] based on a budgeted amount assigned to the given component [para. 0026: “…the signal 221 may additionally include current parameters 220 for the cores, which may be used to set throttling thresholds of the current sensors 112. Values of the current parameters 220 may be set by allocating a power budget that is based on, e.g., based at least in part on, the external voltage regulator overcurrent threshold 105 (FIG. 1).”];
a trigger logic circuit [Fig. 2: PMAs 211] configured to generate a power reduction signal based on receiving trigger signals input to the integrated circuit [para. 0028: “In response to receiving a signal 223 indicating that a measured current exceeds a throttling threshold, the receiving one of the PMAs 211 may determine whether to throttle the corresponding one of the cores 115… The PMAs 211 may send a signal 225, such as a throttle request, to the corresponding core based on the determination. ”], and wherein the power reduction signal applies power control across the plurality of components [Fig. 2 and para. 0028: signal 225 for each respective core, thereby applying power control across the plurality of components];
a rate control circuit configured to control a clock rate for the plurality of components responsive to at least one of the trigger signals [para. 0028: “In some embodiments, the PMAs 211 may determine a degree of throttling (e.g., 10% throttle of the operating frequency) and/or a throttling period (e.g., 100 microseconds), and include parameter information 230 indicating the determined degree and/or period in the throttle request 225 if different than defaults.”]; and
a power management circuit configured to control the budgeted amount assigned to at least one of the plurality of components based on assessment of the power control applied by the power reduction signal against a threshold, wherein the at least one of the plurality of components is configured to manage its power consumption based on the budgeted amount assigned [para. 0031-0031: “…if more than 2.5% of the time a core is throttled (or some other predefined percentage), the PMAs 211 may generate a signal including a hint that too much throttling has been performed. The PCU 297 may utilize the hint to determine whether or not to send an update to the operating characteristics of the cores 115, such as a new lower operating frequency given too much throttling… The hint may also suggest that a portion of a power allocation allocated to a particular core may be reallocated to another component, such as another one of the cores, and/or that a frequency for the core may be increased.”].
Regarding claim 3, Gendler teaches that the rate control circuit is configured to reduce the clock rate responsive to the at least one of the trigger signals [para. 0028: “In some embodiments, the PMAs 211 may determine a degree of throttling (e.g., 10% throttle of the operating frequency)…”].
Regarding claim 4, Gendler teaches that the power management circuit is configured to control the budgeted amount assigned to at least one of the plurality of components by:
detecting whether or not the power control the power control applied by the power reduction signal exceeds the threshold [para. 0031-0031: “…if more than 2.5% of the time a core is throttled (or some other predefined percentage)…”]; and
reducing the budgeted amount assigned to the at least one of the plurality of components based on the power control applied by the power reduction signal exceeding the threshold [“…The hint may also suggest that a portion of a power allocation allocated to a particular core may be reallocated to another component, such as another one of the cores, and/or that a frequency for the core may be increased.”].
Regarding claim 6, because Gendler teaches that throttling controls a current used by the cores [para. 0021, “…thereby locally controlling current utilization by the cores 115…”], it necessarily follows that controlling power in a component of the circuit (i.e., the cores) also controls total power of the circuit. In this manner, Gendler teaches that total power consumption in the integrated circuit is controlled based on the power control applied by the power reduction signal.
Regarding claim 8, Gendler teaches at least one of the components comprises one or more central processing unit (CPU) processors, and wherein the rate control circuit is configured to reduce the clock rate based on receiving the power reduction signal being provided to at least one of the CPUs [para. 0028: “In some embodiments, the PMAs 211 may determine a degree of throttling (e.g., 10% throttle of the operating frequency)…”]. Regarding claim 9, Gendler teaches that the threshold comprises a percentage of time that the power control is applied by the power reduction signal [para. 0031-0031: “…if more than 2.5% of the time a core is throttled (or some other predefined percentage)…”].
Regarding claim 10, Gendler teaches at least one of the components comprises one or more central processing unit (CPU) processors, and wherein the CPU processors are configured to execute a plurality of instructions to implement power control in the integrated circuit using dynamic voltage and frequency control [para. 0025: “The PCU 297 may send a signal 221 including a work point (WP) indicating operating characteristics including voltage and frequency for each core to the PMAs 211.”].
Regarding claim 11, Gendler teaches that the plurality of components comprise one or more of the following: central processing unit (CPU) processors, graphics processing units (GPUs), and peripheral components the plurality of components comprise one or more of the following: central processing unit (CPU) processors, graphics processing units (GPUs), and peripheral components [para. 0004: “A multicore processor is a single computing component with two or more independent processing units, called cores.”].
Regarding claim 12, Gendler discloses an integrated circuit [Fig. 1: multicore processor 110] comprising:
a plurality of components [cores 115], wherein a given component of the plurality of components is configured to manage power consumption [para. 0028: “In response to receiving a signal 223 indicating that a measured current exceeds a throttling threshold, the receiving one of the PMAs 211 may determine whether to throttle the corresponding one of the cores 115.”] based on a budgeted amount assigned to the given component [para. 0026: “…the signal 221 may additionally include current parameters 220 for the cores, which may be used to set throttling thresholds of the current sensors 112. Values of the current parameters 220 may be set by allocating a power budget that is based on, e.g., based at least in part on, the external voltage regulator overcurrent threshold 105 (FIG. 1).”];
a trigger logic circuit [Fig. 2: PMAs 211] configured to generate a power reduction signal based on receiving trigger signals input to the integrated circuit [para. 0028: “In response to receiving a signal 223 indicating that a measured current exceeds a throttling threshold, the receiving one of the PMAs 211 may determine whether to throttle the corresponding one of the cores 115… The PMAs 211 may send a signal 225, such as a throttle request, to the corresponding core based on the determination. ”], and wherein the power reduction signal applies power control across the plurality of components [Fig. 2 and para. 0028: signal 225 for each respective core, thereby applying power control across the plurality of components];
a rate control circuit configured to control a clock rate for the plurality of components responsive to at least one of the trigger signals [para. 0028: “In some embodiments, the PMAs 211 may determine a degree of throttling (e.g., 10% throttle of the operating frequency) and/or a throttling period (e.g., 100 microseconds), and include parameter information 230 indicating the determined degree and/or period in the throttle request 225 if different than defaults.”]; and
a power management circuit configured to control the budgeted amount assigned to at least one of the plurality of components based on assessment of the power control applied by the power reduction signal against a threshold, wherein the at least one of the plurality of components is configured to manage its power consumption based on the budgeted amount assigned [para. 0031-0031: “…if more than 2.5% of the time a core is throttled (or some other predefined percentage), the PMAs 211 may generate a signal including a hint that too much throttling has been performed. The PCU 297 may utilize the hint to determine whether or not to send an update to the operating characteristics of the cores 115, such as a new lower operating frequency given too much throttling… The hint may also suggest that a portion of a power allocation allocated to a particular core may be reallocated to another component, such as another one of the cores, and/or that a frequency for the core may be increased.”];
the power management unit coupled to the integrated circuit [Fig. 2: voltage regulator circuitry 298], wherein the power management unit is configured to supply power to the integrated circuit [para. 0026: “the PMAs 211 may transmit a command 224 to the voltage regulator circuitry 298… to control the cores 115 based on the operating characteristics (e.g., frequency and voltage)”] and to generate the trigger signals [para. 0028: “In response to receiving a signal 223 indicating that a measured current exceeds a throttling threshold, the receiving one of the PMAs 211 may determine whether to throttle the corresponding one of the cores 115…”].
Regarding claim 13, Gendler teaches that the power management unit includes:
a plurality of voltage regulators configured to supply a plurality of supply voltages to the integrated circuit [para. 0026: “…the current sensors 112 may be located in voltage regulator circuitry 298, such as a Fully Integrated Voltage Regulator (FIVR) for each core…”]; and
one or more power delivery trigger circuits coupled to the integrated circuit and the plurality of voltage regulators [para. 0026: “…the current sensors 112 may be located in voltage regulator circuitry 298…”], wherein the power delivery trigger circuits are configured to monitor the plurality of voltage regulators and generate the trigger signals based on electrical load experienced by the plurality of voltage regulators [para. 0028: “In response to receiving a signal 223 indicating that a measured current exceeds a throttling threshold, the receiving one of the PMAs 211 may determine whether to throttle the corresponding one of the cores 115…”].
Regarding claim 14, Gendler teaches that the power management circuit is configured to control the budgeted amount assigned to at least one of the plurality of components by:
detecting whether or not the power control the power control applied by the power reduction signal exceeds the threshold [para. 0031-0031: “…if more than 2.5% of the time a core is throttled (or some other predefined percentage)…”]; and
reducing the budgeted amount assigned to the at least one of the plurality of components based on the power control applied by the power reduction signal exceeding the threshold [“…The hint may also suggest that a portion of a power allocation allocated to a particular core may be reallocated to another component, such as another one of the cores, and/or that a frequency for the core may be increased.”].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 5, 9, 10, 12, 15, and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 6, 10, 14-17, and 20 of U.S. Patent No. 11,853,140 in view of Kling et al., U.S. Patent Application Publication No. 2001/0003207.
Application claim 1 and claim 1 of the ‘140 patent may be compared in the following manner:
Application claim 1:
Patent claim 1:
An integrated circuit, comprising:
a plurality of components, wherein a given component of the plurality of components is configured to manage power consumption based on a budgeted amount assigned to the given component;
a trigger logic circuit configured to generate a power reduction signal based on receiving trigger signals input to the integrated circuit, and wherein the power reduction signal applies power control across the plurality of components;
a rate control circuit configured to control a clock rate for the plurality of components responsive to at least one of the trigger signals; and
a power management circuit configured to control the budgeted amount assigned to at least one of the plurality of components based on assessment of the power control applied by the power reduction signal against a threshold, wherein the at least one of the plurality of components is configured to manage its power consumption based on the budgeted amount assigned.
An integrated circuit comprising:
a plurality of components, wherein a given component of the plurality of components is configured to manage power consumption based on a budgeted amount assigned to the given component;
a global power control circuit coupled to the plurality of components and configured to apply power control across the plurality of components responsive to a trigger input to the integrated circuit, wherein total power consumption in the integrated circuit is reduced based on the power control applied by the global power control circuit; and
a power management circuit configured to:
detect whether or not the power control applied by the global power control circuit exceeds a threshold; and
reduce the budgeted amount assigned to at least one of the plurality of components based on a detection that the power control applied by the global power control circuit exceeded the threshold, wherein the at least one of the plurality of components is configured to manage its power consumption based on the reduction in the budgeted amount assigned.
Application claim 1 and patent claim 1 are not identical. But their differences amount to application claim 1 being a broadened version of patent claim 1 (and therefore patent claim 1 reciting the analogous functions with additional limitations), and variations in nomenclature such as trigger logic (application claim 1) vs. global power control (patent claim 1). Consequently, application claim 1 is anticipated by patent claim 1 with respect to most features, with minor variations in language as described.
Application claim 1 recites a rate control circuit which is not recited in patent claim 1. However, Kling discloses a rate control circuit configured to control a clock rate for the plurality of components responsive to at least one of the trigger signals [para 0019: “In response to receiving this throttle signal, one or more of the ICs reduces its power consumption. For example, for one embodiment of the present invention, a processor of the computer system reduces its core frequency while maintaining a consistent bus frequency in response to receiving the throttle signal.”].
It would have been obvious to one of ordinary skill in the art to combine the teachings of patent claim 1 and Kling by modifying patent claim 1 to include a rate control circuit as taught by Kling. Patent claim 1 teaches that the global power control circuit applies power control to components in response to a trigger input, but does not specify the specific mechanisms of power control. Kling teaches that in response to a throttle signal, a processor may reduce power consumption by reducing its core frequency. Therefore, it would have been obvious to one of ordinary skill in the art to apply the teachings of Kling regarding frequency reduction based on Kling’s additional teaching that frequency reduction results in a reduction of power consumption.
Application claim 1 is also obvious over patent claim 20 in view of Kling. Patent claim 20 represents an obvious variant of patent claim 1 in that it is directed to a medium storing instructions for executing the functions recited in patent claim 1 in a system as recited in patent claim 1.
Application claims 5, 10, 12, 15, and 16 recite the same limitations as patent claims 10, 6, and 14-16, respectively, and are therefore anticipated by the patent claims. Application claim 9 recites the same limitations as patent claims 2 and 17 and is therefore anticipated by the patent claims.
Allowable Subject Matter
Claims 2, 5, 7, and 15-20 would be allowable upon filing of a Terminal Disclaimer and/or rewritten to overcome the rejection based on 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ping et al., U.S. Patent No. 9,348,380, discloses a system that provides a power budget in the form of credits to a plurality of memory devices and throttles the memory devices based on comparison of power consumption to the assigned number of credits [Fig. 4].
Folco et al., U.S. Patent Application Publication No. 2016/0139963, discloses a computer system that allocates resources based on a comparison of power consumption to a threshold [para. 0027, Fig. 2, 3a, 3b].
Chen, U.S. Patent No. 9,250,684, discloses a system that manages power consumption based on a budgeted amount assigned to a given components, and generates a power reductions signal that applied power control across a plurality of components [Fig. 3, 4].
Keusel et al., U.S. Patent No. 9,134,779, discloses a system that provides a power budget in the form of credits to a plurality of IP blocks [Fig. 6-10].
Bailey et al., U.S. Patent Application Publication No. 2015/0177814, discloses a system that detects changes in power consumption at a compute node and performs a re-allocation of a system power budget based on the changes [Fig. 7].
The following references have a common assignee and/or inventors as the present application, and disclose subject matter similar to that of the present application:
Granovsky et al., U.S. Patent No. 11,693,472,
Langlinais et al., U.S. Patent No. 11,960,341.
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