DETAILED ACTION
This office action is in response to communication filed on 03/29/2025. Claims 1-17 are pending on this application.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1, 4-8, and 11-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Funabashi et al. Pub. No. 2020/0106439.
Regarding claim 1. Fig. 4 of Funabashi et al. disclose a transmitter in an interface circuit (121), comprising: a first retimer circuit (210) configured to serialize data (parallel-serial of 210) by interleaving even bits (2 Bit parallel Even numbered bit) of the data and odd bits (2 Bit parallel Odd numbered bit) of the data into a first bitstream (output bitstream of 210); a second retimer circuit (20) configured to serialize the data (parallel-serial of 210) by interleaving even bits of the data (2 Bit parallel Even numbered bit) and inverted versions (20) of the odd bits of the data (2 Bit parallel Odd numbered bit) into a second bitstream (output bitstream of 220) ; and line driver circuits (23, 35) configured to transmit the first bitstream (output bitstream of 210) over a communication link (Communication link of 35).
Regarding claim 4. The interface circuit of claim 1, Fig. 4 further discloses wherein the second retimer circuit (220) is a replica (parallel-serial conversion) of the first retimer circuit (210).
Regarding claim 5. The interface circuit of claim 1, Fig. 4 further disclosews wherein the second retimer circuit (22) comprises replicas (24, 36) of the line driver circuits (23, 25).
Regarding claim 6. The interface circuit of claim 5, wherein the replicas of the line driver circuits (24, 36) are configured to receive the second bitstream (output bit stream of 220) as an input (input of 24).
Regarding clam 8. Fig. 4 of Funabashi et al. disclose a method for reducing jitter (paragraph 0003) in a serial interface (120), comprising: serializing data (210) by interleaving even bits of the data (2 Bit parallel Even numbered bit) and odd bits of the data (2 Bit parallel Odd numbered bit) into a first bitstream (outputs bit stream of 210); serializing (210) the data (N) by interleaving even bits of the data (2 Bit parallel Even numbered bit) and inverted versions (20) of the odd bits of the data (2 Bit parallel Odd numbered bit) into a second bitstream (outputs bitstream of 220) ; and providing the first bitstream (output bitstream of 210) to line driver circuits (23, 35) that are configured to transmit the first bitstream (outputs bitstream of 210) over a communication link (communication link of 35).
Regarding claim 11. The method of claim 8, Fig. 4 further discloses wherein the first bitstream (output of 210) generated by a first retimer circuit (clock timing of 210) and the second bitstream (output of 220) is generated by a second retimer circuit (timing of 220) that is a replica (replica of 220 to 210) of the first retimer circuit (timing of 210).
Regarding claim 12. The method of claim 11, wherein the second retimer circuit (timing of 220 comprises replicas of the line driver circuits (replicas of 24 and 36 to 23 and 35).
Regarding claim 13. The method of claim 12, wherein the replicas of the line driver circuits (24 and 36) are configured to receive the second bitstream (outputs of 220) as an input (input of 24).
Regarding claim 14. Fig. 4 of Funabashi et al. disclose a transmitter in an interface circuit (121), comprising: a data path having a first retimer circuit (data path of clock timing circuit 210) configured to serialize data (parallel-Serial conversion 210) by interleaving even bits of the data (2 Bit parallel Even numbered bit) and odd bits of the data (2 Bit parallel Odd numbered bit) into a first bitstream (outputs bitstream of 210) , and a first plurality of line driver circuits (23, 35) configured to transmit the first bitstream (outputs bitstream of 210) over a communication link (communication link of 35) ; and a compensation path having a second retimer circuit (path of clock timing circuit 220), wherein the second retimer circuit (clock timing of 220) is a replica (parallel-serial conversion of 220) of the first retimer circuit (clock timing of 210).
Regarding claim 15. The interface circuit of claim 14, Fig. 4 further discloses wherein the compensation path (path of clock timing circuit 220) further comprises a second plurality of line driver circuits (24m 36) that are unconnected to the communication link (communication link of 35).
Regarding claim 16. The interface circuit of claim 14, Fig. 4 further discloses wherein the first retimer circuit (timing 0f 210) and the second retimer circuit (timing of 220) are configured to receive a same clock signal from a clock generator (Clock Signal).
Regarding claim 17. The interface circuit of claim 14, Fig. 4 further discloses wherein the compensation path (path of clock timing circuit 220) further comprises an inverter (20) coupled to an input of the second retimer circuit (timing of 220) , the inverter (20) configured to invert (20) the odd bits of the data (2 Bit parallel Odd numbered bit).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Funabashi et al. as applied to claims 1 and 8 above, in further view of Qin et al. Pub. No. 2019/0104088.
Regarding claim 2. Funabashi et al. as applied to claims 1 and 8 above do not discloses wherein the first retimer circuit comprises a first serializer that is configured to serialize the even bits of the data, and a second serializer that is configured to serialize the odd bits of the data.
Fig. 3 of Qin et al. discloses wherein the first retimer circuit (252) comprises a first serializer (Even Serializer of 250) that is configured to serialize the even bits of the data (Even), and a second serializer (Odd Serializer of 250) that is configured to serialize the odd bits of the data (Odd).
Funabashi et al. and Qin are common subject matter of serializer timing of even and odd bits for transmitter; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Qin et al. into Funabashi et al. for the purpose of providing high-speed, full-rate transmitter drivers (paragraph 0001 of Qin et al.).
6. Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Funabashi et al. and Qin et al. applied to claims 2 and 9 above, in further view of Katta et al. U.S. patent 10,892,775.
Funabashi et al. and Qin et al. applied to claims 2 and 9 above do not discloses a multiplexing circuit configured to generate the first bitstream by combining data bits output by the first serializer and data bits output by the second serializer.
Fig. 3 of Katta et al. discloses a multiplexing circuit (306) configured to generate a first bitstream (Seiral Data) by combining (combining of 306) data bits (Even Data) output by the first serializer (304A) and data bits (Odd data) output by the second serializer (304B).
Funabashi et al., Qin et al. and Katta et al. are common subject matter of serializer timing of even and odd bits for transmitter; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Katta et al into Funabashi et al./ Qin et al. for the purpose of providing a multiplexer (306) to generate serial bits stream from combining of even bits and odd bits (Col. 7 lines 55-57 of Katta et al.).
7. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Funabashi et al. applied to claim 1 above in view of Katta et al. U.S. patent 10,892,775,
Funabashi et al. applied to claim 1 above, do not disclose wherein the interface circuit (121) is configured to operate in accordance with a Peripheral Component Interconnect Express (PCIe) protocol.
Fig. 3 of Katta et al. discloses the interface circuit (103) is configured to operate in accordance with a Peripheral Component Interconnect Express (PCIe) protocol (Col. 1 lines 25-30).
Funabashi et al. and Katta et al. are common subject matter of serializer timing of even and odd bits for transmitter; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Katta et al into Funabashi et al. for the purpose of providing high speed interface Express (PCIe) protocol ((Col. 1 lines 25-30 of Katta et al.).
Contact Information
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
10/17/2025
/LINH V NGUYEN/Primary Examiner, Art Unit 2845