DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The Examiner acknowledges Applicant’s arguments and remarks filed on 12 November 2025. They have been fully considered but they are not sufficient to place the claims in condition for allowance. The amendments do not sufficiently address the issues raised in the prior Office Action. Additionally, they have also necessitated new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 has been amended to add the following language: “the first chiplet and the second chiplet are configured to operate in a bypass mode configured to bypass clock modulation enable signals”. The new language is indefinite because it may be interpreted as a statement of intended use, and therefore possibly non-limiting. The Examiner notes that claim 1 is a method claim, whereas the new language does not specifically provide further limitation of the method itself, nor does it meaningfully inform how the method is performed. The Examiner further notes that it conflicts with the established claim limitations because it recites that the first and second chiplets are configured to bypass clock modulation enable signals, while existing language recites that the second chiplet accesses the first clock modulation enable signal and activates a second clock modulation unit based on the first clock modulation enable signal. If the bypass mode is intended as more than a mere intended use, the Examiner recommends amending the claim to more explicitly indicate that the bypass mode features are part of the claimed method. For example, the claim could be amended to add steps such as “configuring the first and second chiplet to operate in a bypass mode” and “in the first chiplet, bypassing the second clock modulation enable signal from the second chiplet based on the bypass mode”1.
Claims 4-8, 12, and 14 are rejected because they recite structural features of elements used in the method that are not clearly related to steps carried out by the method. For example, claim 4 recites that “the first chiplet is configured to operate in the bypass mode comprising a control logic configured to override clock modulation enable signals from the second chiplet”. Claim 4 is directed to a method, whereas this language recites structural limitations that do not clearly further define the method. This language may also therefore be interpreted as a statement of intended use (and possibly non-limiting). It is unclear whether the bypass mode and/or override functions are part of the method recited in claim 1. Similar reasoning may be applied to claims 5-8, 12 (lines 4-6), and 14. The Examiner recommends amending the claim to more explicitly indicate that the bypass mode features are part of the claimed method. For example, claim 4 could be amended to recite “the method further comprises configuring the first chiplet to operate in the bypass mode by configuring a control logic to override clock modulation enable signals from the second chiplet”.
With respect to claims 8, 12, and 14, the limitations appear to be directed purely to structural features of an apparatus that are employed with the method. It is unclear whether they further limit the method itself, or are merely an intended use or an intended result (claim 14: reduced resistance and capacitance).
Claims 4-7 and 15-20 are rejected as being indefinite because they recite a “bypass mode comprising a control logic”. It is unclear how a “mode” (i.e., an abstract state of operation) may comprise control logic (i.e. digital circuitry). The Examiner recommends amending the claims to recite the bypass mode features as additional steps of the method (claims 4-7), or as additional structures of the apparatus (claims 15-20). For example, claim 4 could be amended to recite “the method further comprises configuring the first chiplet to operate in the bypass mode by configuring a control logic to override clock modulation enable signals from the second chiplet”. Claim 15 could be analogously amended to recite “the first chiplet includes a control logic configured to cause the first chiplet to operate in a bypass mode by overriding clock modulation enable signals from the second chiplet”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bose et al., U.S. Patent Application Publication No. 2019/0146568, in view of Swaminathan et al., U.S. Patent Application Publication No. 201/0005665.
Regarding claim 1, Bose discloses a method comprising:
monitoring, at a first droop detector of a first chiplet [Fig. 5: first voltage sensor 122 within first unit 120], voltage levels associated with a shared power supply of the first chiplet and a second chiplet [Fig. 1: first and second unit of processor core 110; para. 0020: “As herein disclosed, integrated circuits (e.g., processors) can receive power from a power source, such as a power supply, to provide a source voltage and a source current for the associated circuitry.”];
the first chiplet and the second chiplet are configured to operate in a bypass mode configured to bypass clock modulation enable signals [intended use, non-limiting];
detecting, a first voltage droop [para. 0044: “This can allow one or more of cores 110-115 to locally determine a response to a detected voltage droop, e.g., detection, validation, and/or mitigation of a voltage droop via sensors local to the particular core.”] that triggers a first clock modulation enable signal [Fig. 5: mitigation decision information 562];
communicating the first clock modulation enable signal to the second chiplet having a second droop detector [Fig. 5: mitigation decision notification information 570; para. 0044: “At 502 of system 500, cores 110-115 can communicate with each other to inform other cores of local mitigation decision notification information, e.g., 570, etc.”];
accessing, at the second chiplet, the first clock modulation enable signal, and based on the first clock modulation enable signal, activating a second clock modulation unit of the second chiplet [para. 0055: “For example, applying the second mitigation technique can comprise applying a second mitigation technique at the first area of the processor core. Further to this embodiment, a third mitigation technique can be applied at a second area of the processor core. The second mitigation technique and the third mitigation technique can be based on respective instructions. In an embodiment, a local instruction received from the local controller, e.g., 126, 136, etc., can be overridden by an instruction received from a global controller, e.g., 140, etc.”].
Bose teaches a droop mitigation technique, but does not explicitly teach that the mitigation technique is a clock modulation.
Swaminathan discloses a droop mitigation technique comprising clock modulation [para. 0027: “At time t1, comparator 122 detects the voltage droop and asserts signal droop_det to cause oscillator circuit 110 to go into an open-loop mode and to output the frequency-divided signal, so that Digital Clock goes to 1 GHz.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Bose and Swaminathan by modifying Bose to employ a droop mitigation technique comprising clock modulation as taught by Swaminathan. Both Bose and Swaminathan are directed to systems that are impacted by voltage droop. Swaminathan teaches that voltage droops can cause timing errors in circuits, and that modulating the clock frequency can avoid such errors [para. 0022-0023: “In one particular example, power delivery network resonance may cause a voltage droop of a magnitude that might otherwise be expected to cause a timing error in a critical path… within one or two clock cycles, system 100 reacts to the voltage drop by dividing the clock frequency by two. The processing cores or other circuits (not shown) receive the clock signal at the lower frequency and thus do not suffer from timing errors while the voltage is low.”]. It would therefore have been obvious to one of ordinary skill in the art to apply the teachings of Swaminathan to Bose based on Swaminathan’s teaching that clock modulation during voltage droop can help avoid timing errors. In combining the Bose and Swaminathan to comply clock modulation as the droop mitigation technique, the mitigation decision information signal may be construed as a clock modulation enable signal.
Regarding claim 3, Swaminathan teaches that the first clock modulation enable signal is communicated to a first frequency divider of the first chiplet and a second frequency divider of the second chiplet [Fig. 1: PLL 110 includes divider 112].
Regarding claim 8, Swaminathan teaches that the first chiplet is coupled to a first PLL and a first clock modulation unit, and the second chiplet is coupled to a second PLL and a second clock modulation unit [Fig. 1: PLL and divider].
Regarding claim 9, Swaminathan teaches activating a first clock modulation unit of the first chiplet based on the first clock modulation enable signal [para. 0027].
Allowable Subject Matter
Claims 10-14 are allowed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov
1 With respect to prior art comparisons, merely reciting a bypass mode by itself would not necessarily overcome the prior art. The broadest reasonable interpretation of a bypass mode would include any and every mode that performs any kind of operation that could be construed as bypassing, including bypassing unrelated to clock modulation enable signals.