DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. More specifically, the foreign priority to KR10-2024-0003945 with a priority date of January 10th, 2024, is acknowledged. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) filed on March 29th, 2024, is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 4 and 7 are objected to because of the following informalities:
a) Regarding Claim 4, the limitation should read, “wherein [[the]] each of the pillars further comprises …”;
a) Regarding Claim 7, the limitation should read, “wherein [[the]] each of the pillars further comprises …”;
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li, et al (CN 204857728 U; hereinafter referred to as Li).
Regarding Claim 1, Li discloses a pillar structure comprising:
a semiconductor layer having a first conductivity type (epitaxial layer 102, [0017], Fig. 4; “N-type epitaxial layer 102”), the semiconductor layer comprising an active region (active region 210, [0080], Fig. 8) and a peripheral region surrounding the active region (voltage divider ring region 211, [0080], Fig. 8; “a voltage divider ring region 211 located on the periphery of the active region”); and
pillars having a second conductivity type (P-type doped region 104, [0020], Fig. 4), the pillars extending in a vertical direction within the semiconductor layer and extending in a horizontal direction across the active region and the peripheral region (Figs. 4, 5, and 8),
wherein each of the pillars comprises an active pillar disposed within the active region (P-type doped region 220, [0074], Fig. 10), a lower peripheral pillar disposed within the peripheral region and connected to the active pillar (bifurcated portions 222, [0031, 0083], Figs. 9-10; while Fig. 10 shows the bifurcated portions disposed within the active region, Fig. 9 shows that they also can occur in the peripheral region), and a pair of upper peripheral pillars disposed on the lower peripheral pillar and branching from the active pillar (second P-type doped region 221, [0083], Figs. 9-10),
the pair of upper peripheral pillars branch from an interface between the active region and the peripheral region (Fig. 9), and comprise a pair of connecting portions connected to the active pillar (bifurcated portions 222, [0083], Figs. 9-10) and a pair of extending portions each extending in the horizontal direction from the pair of connecting portions (second P-type doped region 221, [0083], Figs. 9-10), and
the pair of connecting portions are spaced apart from each other on the interface (Figs. 9-10).
Regarding Claim 2, Li discloses the pillar structure of claim 1, further comprising:
body regions having the second conductivity type and each disposed between an upper surface of the semiconductor layer and the pillars (body region 103, 206, [0004, 0103], Figs. 4 and 23; “a P-type doped body region 206”).
Regarding Claim 3, Li discloses the pillar structure of claim 1, wherein a distance between the pair of connecting portions gradually increases in the horizontal direction (Figs. 9-10).
Regarding Claim 4, Li discloses the pillar structure of claim 1, wherein the each of the pillars further comprises a pair of expanding portions disposed within the active region and connecting the connecting portions and the active pillar (bifurcated portion 322, [0110], Fig. 26).
Regarding Claim 5, Li discloses a super junction semiconductor device comprising:
a substrate having a first conductivity type (substrate 201, [0088]; “The semiconductor substrate 201 may be, for example, an N-type heavily doped (N+) silicon substrate”);
a semiconductor layer having the first conductivity type and disposed on the substrate (epitaxial layer 2021, [0088]; “the meso epitaxial layer 2021 may be an N-type lightly doped (N-) layer”), the semiconductor layer comprising an active region (active region 220, [0085], Fig. 8) and a peripheral region surrounding the active region (voltage divider ring region 211, [0080], Fig. 8; “a voltage divider ring region 211 located on the periphery of the active region”);
pillars having a second conductivity type (P-type doped region 104, [0020], Fig. 4), the pillars extending in a vertical direction within the semiconductor layer and extending in a horizontal direction across the active region and the peripheral region (Figs. 4, 5, and 8); and
body regions having the second conductivity type and each disposed between an upper surface of the semiconductor layer and the pillars (body region 103, 206, [0004, 0103], Figs. 4 and 23; “a P-type doped body region 206”),
wherein each of the pillars comprises an active pillar disposed within the active region (P-type doped region 220, [0074], Fig. 10), a lower peripheral pillar disposed within the peripheral region and connected to the active pillar (bifurcated portions 222, [0031, 0083], Figs. 9-10; while Fig. 10 shows the bifurcated portions disposed within the active region, Fig. 9 shows that they also can occur in the peripheral region), and a pair of upper peripheral pillars disposed on the lower peripheral pillar and branching from the active pillar (second P-type doped region 221, [0083], Figs. 9-10)
the pair of upper peripheral pillars branch from an interface between the active region and the peripheral region (Fig. 9), and comprise a pair of connecting portions connected to the active pillar (bifurcated portions 222, [0083], Figs. 9-10) and a pair of extending portions each extending in the horizontal direction from the pair of connecting portions (second P-type doped region 221, [0083], Figs. 9-10), and
the pair of connecting portions are spaced apart from each other on the interface (Figs. 9-10).
Regarding Claim 6, Li discloses the super junction semiconductor device of claim 5, wherein a distance between the pair of connecting portions gradually increases in the horizontal direction (Figs. 9-10).
Regarding Claim 7, Li discloses the pillar structure of claim 5, wherein the each of the pillars further comprises a pair of expanding portions disposed within the active region and connecting the connecting portions and the active pillar (bifurcated portion 322, [0110], Fig. 26).
Regarding Claim 8, Li discloses the super junction semiconductor device of claim 5, further comprising:
gate electrodes extending in the horizontal direction and disposed on the semiconductor layer between the body regions (gate structure 106, gate structure 208, [0004, 0101], Figs. 4 and 23; “gate structure 208 may include . . . a gate electrode”);
gate insulating layers disposed between the semiconductor layer and the gate electrodes (gate structure 106, gate structure 208, [0004, 0101], Figs. 4 and 23; “gate structure 208 may include a gate dielectric layer (e.g., silicon oxide)”; dielectric layers are insulating layers); and
source regions disposed in surface portions of the body regions (source region 105, [0004, 0103], Fig. 4).
Regarding Claim 13, Li discloses the super junction semiconductor device of claim 5, wherein the semiconductor layer further comprises a transition region disposed between the active region and the peripheral region (transition region, [0076], “Within the transition region (e.g., the transition region is located at the edge of the active region 210) that connects the active region 210 and the voltage divider ring region 211 …”), and
the pillars extend across the transition region in the horizontal direction ([0076-0077]).
Regarding Claim 15, Li discloses the super junction semiconductor device of claim 13, further comprising:
second pillars having the second conductivity type (second P-type doped region 221, [0083], Figs. 9-10), the second pillars extending in the vertical direction and the horizontal direction within a portion of the peripheral region disposed on one side of the transition region (Figs. 9-11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(a) Determining the scope and contents of the prior art.
(b) Ascertaining the differences between the prior art and the claims at issue.
(c) Resolving the level of ordinary skill in the pertinent art.
(d) Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9-12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li as applied to Claims 1-8, 13, and 15 above, and further in view of Lee, et al (US 20220069075 A1; hereinafter referred to as Lee).
Regarding Claim 9, Li discloses the super junction semiconductor device of claim 8.
Li does not disclose wherein the body regions comprise first body regions disposed in the active region and second body regions disposed in the peripheral region, and the source regions are disposed in surface portions of the first body regions.
However, in analogous art, Lee discloses a super junction semiconductor device (super junction semiconductor device 100), wherein the body regions comprise first body regions disposed in the action region (P-body region 146, [0058], Fig. 6) and second body regions disposed in the peripheral region (P-top region 153, [0086], Fig. 6), and
the source regions (high concentration region 147) are disposed in surface portions of the first body regions (Fig. 6; no source region is provided for the peripheral region).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the super junction device as disclosed by Li by having different body regions for active and peripheral pillars, and only having the source regions be with the first body regions as disclosed by Lee. One would be motivated to do so as the modification as taught by Lee allows for an electrical connection between active pillars and a source electrode located on top of the pillar structure, which leads to the source electrode being more stably secured and providing greater structural support to the device (Lee: [0058]).
Regarding Claim 10, Li/Lee discloses the super junction semiconductor device of claim 9, further comprising:
an interlayer insulating layer disposed on the gate electrodes and the body regions (Lee: interlayer insulating layer, [0111]; “an insulating interlayer (not shown) is further formed through a deposition process and a reflow process. Thereafter, the insulating interlayer and the gate oxide layer are patterned to form contact openings (not shown) exposing the high concentration region”);
a source electrode disposed on the interlayer insulating layer (Lee: source electrode 190, [0087], 0112], Fig. 3); and
source contacts connecting the source electrode and the source regions through the interlayer insulating layer (Lee: [0111], “Thereafter, the insulating interlayer and the gate oxide layer are patterned to form contact openings (not shown) exposing the high concentration region”).
Regarding Claim 11, Li/Lee discloses the super junction semiconductor device of claim 10, wherein the source contacts are connected to the first body regions through the source regions (Lee: [0112]).
Regarding Claim 12, Li/Lee discloses the super junction semiconductor device of claim 10, further comprising:
body contacts connecting the source electrode and the second body regions through the interlayer insulating layer (Lee: [0112]).
Regarding Claim 14, Li discloses the super junction semiconductor device of claim 13.
Li does not disclose wherein the pillars further comprise transition pillars disposed in the transition region, a diffusion region having the second conductivity type is disposed on the transition pillars, and a reverse recovery region having the second conductivity type and an impurity concentration higher than that of the diffusion region is disposed on the diffusion region.
However, in analogous art, Lee does disclose wherein the pillars further comprise transition pillars disposed in the transition region (transition pillars 132, [0053], Fig. 6; “transition pillars 132 provided in the transition region TR”),
a diffusion region having the second conductivity type is disposed on the transition pillars (diffusion region 148, [0070, 0071], Fig. 6; “The diffusion region 148 in the transition region TR may have the second conductivity type as the P-body region 146 in the active region has”), and
a reverse recovery region having the second conductivity type and an impurity concentration higher than that of the diffusion region is disposed on the diffusion region (reverse recovery layer 140, [0067, 0069, 0072], Fig. 6; “The reverse recovery layer 140 may have a second conductivity type, for example, a P-type conductivity”, “Meanwhile, the reverse recovery layer 140 may have the ion concentration higher than that of the diffusion region 148”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the super junction device as disclosed in Li by introducing specific transition pillars containing a diffusion region and a reverse recovery region. One would be motivated to add the diffusion and reverse recovery region in order to connect the transition pillar to the source electrode through the diffusion and reverse recovery region, which provides the benefit of effectively reducing the resistance experienced between the source electrode and the transition pillar and suppresses the reverse recovery phenomenon (Lee: [0005-0006, 0070-0072]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li as applied to Claims 1-8, 13, and 15 above, and further in view of Lee, et al. (US 20220069075 A1; hereinafter referred to as Lee) and further in view of Motai, et al. (US 2024/0097021 A1; hereinafter referred to as Motai).
Regarding Claim 16, Li/Lee discloses the super junction semiconductor device of claim 15.
Li/Lee fails to disclose wherein a second diffusion region having the second conductivity type is disposed on a second pillar adjacent to the transition region among the second pillars, and a reduced surface field region having the second conductivity type and having an impurity concentration lower than that of the second diffusion region is disposed on remaining second pillars.
However, in analogous art, Motai discloses wherein a second diffusion region (first diffusion layer 301) having the second conductivity type is disposed on a second pillar adjacent to the transition region among the second pillars (Motai: [0025, 0036]), and
a reduced surface field region (RESURF layer 311) having the second conductivity type and having an impurity concentration lower than that of the second diffusion region is disposed on remaining second pillars (Motai: [0025, 0036]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the super junction semiconductor device as taught by the combination of Li/Lee by applying a second diffusion region having the second conductivity type on a second pillar adjacent to the transition region among the second pillars and to apply a RESURF region on the remaining second pillars as taught by Motai. One would be motivated to do so as applying a RESURF layer with a lower impurity concentration than that of the diffusion region leads to little or no depletion to current when there is a high voltage applied to the device, which leads to increased device performance (Motai: [0043]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Wang, et al. (US 2023/0282696 A1); discloses an analogous super-junction device with active and peripheral pillars.
(b) Tseng, et al. (US 2024/0128381 A1); discloses an analogous super-junction device teaching that the RESURF layer is interchangeable with the diffusion region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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