DETAILED ACTION
This Office Action is in response to the divisional application filed on 29 March 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 10-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kariya (US 2020/0098785 A1; hereinafter Kariya).
In regards to claim 1, Kariya teaches, e.g. in figs. 4-6, an electronic device comprising:
a stack of alternating dielectric materials (31) and conductive materials (34a/34b) ([0155-0164]; figs. 10-12); and
one or more pillars (MP1) in the stack [0170], the one or more pillars comprising:
an oxide material (40A) laterally adjacent to the dielectric materials and the conductive materials (e.g. fig. 10: (40A) is laterally adjacent to (31) and (34a/34b) in the x direction);
a storage node (evidenced by storage film (40B) along C-C') comprising a charge confinement region (40B) and peripheral regions (e.g. 41), the charge confinement region between vertically adjacent portions of the oxide material and laterally adjacent to the conductive materials of the stack (fig. 10);
a tunnel material (40C) laterally adjacent to the storage node [0134]; and
a channel material (41) laterally adjacent to the tunnel material [0137].
In regards to claim 2, Kariya teaches the limitations discussed above in addressing claim 1. Kariya further teaches, e.g. in figs. 4-6, the limitations wherein the oxide material (40A) and the storage node (40B) are continuous materials in a vertical direction (fig. 6) [0134].
In regards to claim 3, Kariya teaches the limitations discussed above in addressing claim 1. Kariya further teaches the limitations wherein a portion of the oxide material (40A) is between vertically adjacent dielectric materials (31) of the stack (e.g. fig. 4: elements (40A) exists in planes between elements (31) between (34)).
In regards to claim 4, Kariya teaches the limitations discussed above in addressing claim 3. Kariya further teaches, e.g. in figs. 4-6, the limitations wherein the portion of the oxide material (40A) between the vertically adjacent dielectric materials (31) of the stack is proximal to the conductive materials (34) and the vertically adjacent portions of the oxide material are distal to the conductive materials (fig. 4).
In regards to claim 10, Kariya teaches, e.g. in figs. 14-35, a system, comprising:
a processor operably coupled to an input device and an output device ([0080]: inferred by (1) being NAND memory device) (fig. 1); and
a memory device (1) operably coupled to the processor and comprising at least one electronic device, the at least one electronic device comprising:
strings of memory cells (11) vertically extending through a stack of alternating dielectric materials (31) and conductive materials (34a/34b) ([0155-0164]; figs. 10-12);
a channel region (41) within a pillar region of the at least one electronic device [0137];
a tunnel region (40C) adjacent to the channel region within the pillar region [0134];
a storage node region (evidenced by storage film (40B) along C-C') adjacent to the tunnel region and extending continuously along a vertical direction of the pillar region (fig. 6) [0134], the storage node region comprising charge confinement regions (40B) in horizontal alignment with the conductive materials of the stack without being in horizontal alignment with the dielectric materials of the stack (fig. 10); and
an oxide material (40A) between the dielectric materials and the conductive materials of the stack and the storage node region (e.g. fig. 10: (40A) is laterally adjacent to (31) and (34a/34b) in the x direction).
In regards to claim 11, Kariya teaches the limitations discussed above in addressing claim 10. Kariya further teaches, e.g. in figs. 14-35, the limitations wherein the channel region comprises portions extending farther into a central portion of the pillar region relative to additional portions of the channel region, each of the portions and the additional portions of the channel region are substantially symmetric with respect to a central axis of a pillar along the vertical direction of the pillar region (fig. 10: the portion of (40A) laterally adjacent to (31) protrudes further into core (42) than the portion of (40A) laterally adjacent to (34a/34b)).
In regards to claim 12, Kariya teaches the limitations discussed above in addressing claim 10. Kariya further teaches, e.g. in figs. 14-35, the limitations further comprising an insulative material in a central portion of the pillar region, wherein an outer diameter of a portion of the insulative material at an elevation of the conductive materials of the stack is greater than an outer diameter of another portion of the insulative material at an elevation of the dielectric materials of the stack (e.g. fig. 27: increasing diameter when moving away from the substrate in the z-axis).
In regards to claim 13, Kariya teaches the limitations discussed above in addressing claim 10. Kariya further teaches, e.g. in figs. 14-35, the limitations wherein a continuous portion of the oxide material surrounds a continuous portion of the storage node region, the oxide material directly contacting the storage node region of the pillar region and the dielectric materials and the conductive materials of the stack (e.g. fig. 6).
In regards to claim 14, Kariya teaches the limitations discussed above in addressing claim 12. Kariya further teaches, e.g. in figs. 14-35, the limitations wherein the another portion of the insulative material (e.g. portions of (31) intervenes between vertically neighboring portions of the channel material (fig. 17).
In regards to claim 15, Kariya teaches the limitations discussed above in addressing claim 10. Kariya further teaches the limitations further comprising a conductive liner material at least partially surrounding individual portions of the conductive materials of the stack, the conductive liner material laterally recessed relative to inner sidewalls of the dielectric materials of the stack (fig. 60: e.g. (40Aa) versus (40Ab)).
In regards to claim 16, Kariya teaches the limitations discussed above in addressing claim 1. Kariya further teaches, e.g. in figs. 14-35, the limitations wherein a material composition of the oxide material is substantially the same as a material composition of the dielectric materials of the stack (31) [0121].
In regards to claim 17, Kariya teaches the limitations discussed above in addressing claim 1. Kariya further teaches, e.g. in figs. 14-35, the limitations wherein a single portion of the oxide material directly intervenes between the storage node and the alternating dielectric materials and conductive materials of the stack (fig. 17: e.g. portions of (31).
In regards to claim 18, Kariya teaches the limitations discussed above in addressing claim 1. Kariya further teaches, e.g. in figs. 14-35, the limitations wherein the oxide material comprises varying thicknesses along a vertical extent of the stack (e.g. fig. 27: increasing diameter when moving away from the substrate in the z-axis).
In regards to claim 19, Kariya teaches the limitations discussed above in addressing claim 5. Kariya further teaches, e.g. in figs. 14-15, the limitations further comprising forming a sacrificial oxidized nitride material using portions of the nitride materials of the stack prior to forming the oxide material (50) (fig. 15; [0167]).
In regards to claim 20, Kariya teaches the limitations discussed above in addressing claim 5. Kariya further teaches, e.g. in figs. 14-35, the limitations further comprising:
forming a channel material (41) adjacent to the storage node (evidenced by storage film (40B) along C-C'); and
forming a plug material (e.g. CP1) adjacent to the channel material, portions of the channel material directly physically contacting lateral side surfaces of the plug material [0115].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya in view of Or-Bach et al. (US 2020/0013791 A1; hereinafter Or-Bach).
In regards to claim 5, Kariya teaches, e.g. in figs. 14-35, a method of forming an electronic device, comprising:
forming a stack comprising vertically alternating dielectric materials (31) and nitride materials (50) (fig. 15; [0167]);
forming pillar openings (51) in the stack (fig. 17; [0168]);
forming recesses in the nitride materials adjacent to the pillar openings (fig. 46);
forming an oxide material (40A) laterally adjacent to the dielectric materials and in the recesses of the nitride materials [0175];
forming a storage node (40B) along C-C') laterally adjacent to the oxide material, the storage node comprising charge confinement regions (40B) in horizontal alignment with the nitride materials of the stack without being in horizontal alignment with the dielectric materials of the stack (fig. 35).
Kariya appears to be silent as to, but does not preclude, the limitations selectively removing portions of the oxide material without substantially removing portions of the dielectric materials of the stack. Or-Bach teaches the limitations selectively removing portions of the oxide material without substantially removing portions of the dielectric materials of the stack (figs. 3). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kariya with the aforementioned limitations taught by Or-Bach to form memory elements with vertical channels (Or-Bach [0002]).
In regards to claim 6, the combination of Kariya and Or-Bach teaches the limitations discussed above in addressing claim 5. Or-Bach further teaches the limitations wherein forming the oxide material comprises conformally forming a portion of the oxide material adjacent to the dielectric materials and the nitride materials of the stack, sidewalls of the oxide material comprising recessed portions corresponding to the recesses in the nitride materials of the stack (figs. 3). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kariya with the aforementioned limitations taught by Or-Bach to form memory elements with vertical channels (Or-Bach [0002]).
In regards to claim 7, the combination of Kariya and Or-Bach teaches the limitations discussed above in addressing claim 5. Or-Bach further teaches the limitations wherein forming the storage node comprises forming a continuous silicon nitride charge trapping material in the pillar openings, with the oxide material and the storage node being substantially coextensive (figs. 3). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kariya with the aforementioned limitations taught by Or-Bach to form memory elements with vertical channels (Or-Bach [0002]).
In regards to claim 8, the combination of Kariya and Or-Bach teaches the limitations discussed above in addressing claim 5. Or-Bach further teaches the limitations wherein forming the stack comprises forming a barrier material comprising a carbon-doped oxide material adjacent to the dielectric materials of the stack, and wherein selectively removing portions of the oxide material comprises substantially shielding the dielectric materials of the stack with the barrier material (figs. 3). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kariya with the aforementioned limitations taught by Or-Bach to form memory elements with vertical channels (Or-Bach [0002]).
In regards to claim 9, the combination of Kariya and Or-Bach teaches the limitations discussed above in addressing claim 5. The combination of Kariya and Or-Bach appears to be silent as to the limitation of a height of the charge confinement regions in the vertical direction by between about 5 nm and about 20 nm; however Kariya teaches the limitation of different dimensions of memory cell elements to affect threshold voltage and electrical characteristics of a memory device ([0194], [0256]). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the limitation of a height of the charge confinement regions in the vertical direction by between about 5 nm and about 20 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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