Prosecution Insights
Last updated: April 19, 2026
Application No. 18/622,696

SYSTEMS AND METHODS FOR PREEMPTIVE DETECTION AND MITIGATION OF CHIPLET LINK FAILURES

Non-Final OA §102
Filed
Mar 29, 2024
Examiner
CHASE, SHELLY A
Art Unit
2112
Tech Center
2100 — Computer Architecture & Software
Assignee
Ati Technologies Ulc
OA Round
2 (Non-Final)
95%
Grant Probability
Favorable
2-3
OA Rounds
2y 3m
To Grant
98%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
715 granted / 755 resolved
+39.7% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
17 currently pending
Career history
772
Total Applications
across all art units

Statute-Specific Performance

§101
13.2%
-26.8% vs TC avg
§103
38.2%
-1.8% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
15.9%
-24.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 755 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1 to 20 are presented for examination. The amendment filed 10-17-2025 cancelled claims 2 and 13. Allowable Subject Matter Prosecution on the merits of this application is reopened on claim 20 considered unpatentable for the reasons indicated below: Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 20 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Diggs et al. (USPAP 2009/0204852 A1). Claim 20: Diggs substantially teaches the claimed invention. Diggs teaches a storage subsystem that uses solid-state memory devices and a method and an apparatus for assessing a risk of a storage subsystem failure, the apparatus comprising: a controller (114) of a storage subsystem (112) monitoring data (121) of a nonvolatile memory device wherein the monitored data describes the stability of the power signal from the host (see par. 0023). Diggs teaches that the controller may analyze the stored monitor data to assess a risk level associated with the occurrence of data errors (see par. 0026). Diggs teaches that the controller analyzes the stored monitor data to maintain bit error statistics by monitoring a particular variable, which reads on “measuring, by at least one processor, a bit error rate of at least one communications channel between two or more semiconductor processing units” (see par. 0027). Diggs teaches that maintaining bit error statistics comprises measuring a short-term bit error rate (BER) such as “BER since last power up” (see par. 0030). Diggs teaches that the storage subsystem includes one or more sensors (125) that senses various conditions such as temperature, humidity, altitude, and/or storage subsystem movement (see par. 0022). Diggs teaches that the monitor data stored is generated by one or more sensors of the host system and the host-generated sensor data may supplement subsystem-generated sensor data (see par. 0033). Diggs teaches that a process (300) to collect and analyze the monitor data (see fig 3) having a monitoring operating and/or environment conditions state (321) monitoring data and storing the monitored data in step (322) (see par. 0050). Diggs teaches that at state (323) the risk level of the monitored data is analyzed and at state (324) the risk level is determined based on if it is greater than a predetermined or correlated-based threshold (see par. 0051). Diggs teaches that at state (325) an alert is generated when the conditions are met for the risk level greater than the predetermine threshold and monitoring continues in the background (see par. 0052). Digs teaches that if high BER occurs when operating temperature exceeds a particular threshold, it may adjust the temperature threshold used to generate alert messages or cause the controller to slow its operation (see par. 0032). Allowable Subject Matter Claims 1, 3 to 12 and 14 to 19 are allowed. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272 3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Shelly A Chase/Primary Examiner, Art Unit 2112
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Prosecution Timeline

Mar 29, 2024
Application Filed
Jun 13, 2025
Non-Final Rejection — §102
Oct 01, 2025
Applicant Interview (Telephonic)
Oct 01, 2025
Examiner Interview Summary
Oct 17, 2025
Response Filed
Feb 20, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603144
BLOCK HEALTH DETECTOR FOR BLOCK RETIREMENT IN A MEMORY SUB-SYSTEM
2y 5m to grant Granted Apr 14, 2026
Patent 12603753
SIGNAL TRANSMITTING METHOD, ELECTRONIC DEVICE, AND COMMUNICATION SYSTEM
2y 5m to grant Granted Apr 14, 2026
Patent 12596610
PARITY DATA IN DYNAMIC RANDOM ACCESS MEMORY (DRAM)
2y 5m to grant Granted Apr 07, 2026
Patent 12572413
MEMORY CONTROLLERS AND MEMORY SYSTEMS
2y 5m to grant Granted Mar 10, 2026
Patent 12572412
MANAGING ERROR CORRECTIONS FOR DATA STORAGE SYSTEMS
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
95%
Grant Probability
98%
With Interview (+3.3%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 755 resolved cases by this examiner. Grant probability derived from career allow rate.

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