Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 11-14, 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Davis, US Patent 6,367,003 (hereinafter Davis) in view of Park et al., “Resource Recycling: Putting Idle Resources to Work on a Composable Accelerator” (hereinafter Park).
Regarding claim 1, Davis teaches:
A device comprising: a processing element configured to receive a first set of vectors (see e.g. fig. 4B, 8B, col. 5 lines 7-17, col. 7 lines 4-24, vector data is received on buses); and a hijack control circuit configured to determine that the processing element is idle (see e.g. col. 2 lines 1-7, col. 7 lines 50-64, an idle status is determined and control is given to the fixed function circuit during idle times).
Davis fails to explicitly teach wherein based on a determination that the processing element is idle, the processing element is further configured to replace the first set of vectors with a second set of vectors.
Park teaches dynamically partitioning processor elements for tasks such that “resources sitting idle in one stage can be utilized by neighboring stages through resource borrowing” (see pg. 23, section 2.1.3). Therefore a task (and its corresponding data) is replaced with another task and its data due to an element being idle (see e.g. pg. 27, fig. 7).
One would have recognized that the swapping of tasks such as in Park would include the swapping of data for those tasks, and would readily apply to the swapping of vectors such as those of Davis. Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Davis and Park such that based on a determination that the processing element is idle, the processing element is further configured to replace the first set of vectors with a second set of vectors. This would have provided an advantage of increased throughput by using idle resources such as discussed by Park (see e.g. pg. 21 Abstract).
Regarding claim 2, Davis in view of Park teaches or suggests:
The device of claim 1, the processing element comprising a multiplier configured to multiply a set of vectors (see e.g. Davis col. 7 lines 4-18, col. 12 lines 3-27).
Regarding claim 3, Davis in view of Park teaches or suggests:
The device of claim 1, the processing element further comprising: a first multiplexer having an output coupled to an input of a processing device of the processing element, the first multiplexer including: a first input for receiving the first set of vectors, a second input for receiving the second set of vectors, and a control input connected to the hijack control circuit; a register connected to an output of the processing device; and a second multiplexer, the second multiplexer including: a first input for receiving an output of the first multiplexer, a second input for receiving an output of the register, and a control input connected to the hijack control circuit (see e.g. Davis fig. 8A-B, a multiplexer controls input values, which can be controlled to swap such as in Park pg. 23).
Regarding claim 4, Davis in view of Park teaches or suggests:
The device of claim 1, wherein an output of a processing device of the processing element is connected to an input of a processing element control circuit (see Davis e.g. fig. 8B).
Regarding claim 5, Davis in view of Park teaches or suggests:
The device of claim 4, wherein the processing element control circuit comprises processing element control logic configured to determine that a hijack control signal from the hijack control circuit is active, indicating that the processing element is idle (see e.g. fig. 4B, 8B, col. 5 lines 7-17, col. 7 lines 4-24, col. 13 lines 17-31; Park pg. 23).
Regarding claim 6, Davis in view of Park teaches or suggests:
The device of claim 5, wherein the processing element control circuit further comprises a table of stored vectors, and further wherein the processing element control logic is configured to, in response to a determination that the hijack control signal is active, send at least two vectors from the table of stored vectors to the processing element (see e.g. Park pg. 25, a set of candidate task groups is generated, and more than one can be sent to a processing element).
Regarding claim 7, Davis in view of Park teaches or suggests:
The device of claim 6, wherein the processing element control circuit is further configured to insert an output value associated with the second set of vectors into the table of stored vectors and upload the output value to a remote data source (see e.g. Davis col. 10 lines 45-59, data can be output to an external memory).
Claims 11-14, 16-17 are rejected for reasons corresponding to those given above for claims 1-7.
Claims 18-19 are rejected for reasons corresponding to those given above for claims 1, 4-6 (see e.g. Davis fig. 3, 5, output data can be written back to the same area as input data such as memory 502 as a table).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Davis in view of Park, further in view of Bae et al., US Patent Application Publication 2015/0029233 (hereinafter Bae).
Regarding claim 8, Davis in view of Park teaches or suggests:
The device of claim 1.
Davis in view of Park fails to explicitly teach wherein the determination that the processing element is idle comprises the hijack control circuit configured to detect that a previous output of the processing device is the same as a current output of the processing device.
Bae teaches using a comparator circuit to indicate inactivity by comparing previous data from a buffer circuit with current data to determine whether they are the same, wherein the comparator circuit comprises a first input for receiving data and a second input connected to an output of a storage element (see e.g. para. [0129-132]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Davis, Park, and Bae such that the determination that the processing element is idle comprises the hijack control circuit configured to detect that a previous output of the processing device is the same as a current output of the processing device. This would have provided a way of quickly detecting that a device is inactive so that it could be used for other processing to more fully utilize resources such as in Davis.
Regarding claim 9, Davis in view of Park teaches or suggests:
The device of claim 1.
Davis in view of Park fails to explicitly teach wherein the hijack control circuit comprises a first register and a comparator circuit, wherein: the first register receives the first set of vectors; and the comparator circuit has a first input for receiving the first set of vectors and a second input connected to an output of a second register, an output of the comparator circuit comprising a signal causing the processing element to replace the first set of vectors with the second set of vectors.
Bae teaches using a comparator circuit to indicate inactivity by comparing previous data from a buffer circuit with current data to determine whether they are the same, wherein the comparator circuit comprises a first input for receiving data and a second input connected to an output of a storage element (see e.g. para. [0129-132]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Davis, Park, and Bae such that the hijack control circuit comprises a first register and a comparator circuit, wherein: the first register receives the first set of vectors; and the comparator circuit has a first input for receiving the first set of vectors and a second input connected to an output of a second register, an output of the comparator circuit comprising a signal causing the processing element to replace the first set of vectors with the second set of vectors. This would have provided a way of quickly detecting that a device is inactive so that it could be used for other processing to more fully utilize resources such as in Davis.
Claims 10, 15, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Davis in view of Park, further in view of Gu et al., US Patent Application Publication 2020/0184001 (hereinafter Gu).
Regarding claim 10, Davis in view of Park teaches or suggests:
The device of claim 1.
Davis in view of Park fails to explicitly teach wherein the first set of vectors comprises a set of outputs from a layer of a neural network.
Gu teaches performing MAC operations on vector data for neural network training (see e.g. para. [0003], [0039], [0044])
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Davis, Park, and Gu such that the first set of vectors comprises a set of outputs from a layer of a neural network. This would have provided the clearly predictable result of performing the same processing merely on data from a different source. This would have also provided an advantage discussed in Gu that “Deep neural networks are considered as a promising approach to realizing artificial intelligence, and have demonstrated their effectiveness in a number of applications” (see para. [0003]).
Regarding claim 15, Davis in view of Park teaches or suggests:
The device of claim 14.
Davis in view of Park fails to explicitly teach wherein the processing element control circuit further comprises cloud interface logic configured to communicate with the remote data source.
Gu teaches connecting to remote machines through a network interface to the internet (see e.g. para. [0109]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Davis, Park, and Gu such that the processing element control circuit further comprises cloud interface logic configured to communicate with the remote data source. This would have provided an advantage of increased flexibility and control of programming the system through a network.
Claim 20 is rejected for reasons corresponding to those given above for claim 15.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11,947,959. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the instant application are similar to and principally generic to the claims in the ‘959 patent. Therefore, a patent to the genus would improperly extend the right to exclude granted by a patent to the species or sub-genus should the genus issue as a patent after the species or sub-genus (see MPEP 804(II)(B)(1)).
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mei et al., US Patent Application 2015/0095914, teaches swapping the data for active and inactive threads.
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
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