DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Cignoli et al. (EP 4170906 and Cignoli hereinafter)
Regarding claim 1, Cignoli discloses a circuit [fig. 3], comprising: a first switch [QLS] having first [source] and second current terminals [drain] and a first control terminal [gate], in which the first current terminal is coupled to a switch output [VO]; a second switch [MLS] having third [drain] and fourth current terminals [source] and a second control terminal [gate], in which the second control terminal is coupled to the first control terminal, and the fourth current terminal is coupled to the switch output; and a switch network [S2] coupled between the second current terminal of the first switch and the third current terminal of the second switch, the switch network configurable to electrically connect [when switch S2 closes] the second current terminal of the first transistor to the third current terminal of the second transistor and electrically disconnect [when switch S2 open] the second current terminal of the first transistor from the third current terminal of the second transistor.
Regarding claim 2, Cignoli discloses [fig. 3] further comprising a third switch [BS] having fifth [drain] and sixth current terminals [source] and a third control terminal [gate], in which the fifth current terminal is coupled to a voltage supply terminal [terminal 14], and the sixth current terminal is coupled to the first current terminal of the first switch [through S4].
Claim 12 is rejected under 35 U.S.C. 102(a) (1) as being anticipated by Williams (WO 2009020535 A1).
Regarding claim 12, Williams discloses a circuit [figs. 7C and fig. 8], comprising: a first transistor [403A] configured to conduct current through the first transistor between first and second current terminals [source/drain terminals] thereof responsive to a control signal [VG₂] at a control input [gate 403A] of the first transistor having a first value [VG2 value]; a second transistor [403B] coupled to the first transistor and configured to provide a sensor signal [I sense] at a sensor output [Id2], the sensor signal representative of the current through the first transistor responsive to the control signal; and a switch network [404] coupled between at least one terminal of the second transistor and at least one terminal of the first transistor responsive to the control signal having a second value [see fig. 8].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cignoli et al.
Regarding claim 3, Cignoli discloses all the features with respect to claim 1 as indicated above. Cignoli further discloses [fig. 3] wherein: the first switch [FET QLS] comprises a first field effect transistor (FET), the third switch comprises a third FET [FET BS], the first and fifth current terminals are respective drains, the second and sixth current terminals are respective sources, and the first and third control terminals are respective gates. Cignoli does not explicitly disclose the first terminal is drain terminal. It would have been matter of design choice to provide a transistor terminal in order to generate the desired output signal at a selected terminal. Since such a modification would have generally recognized as being within the level of ordinary skill in the art.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cignoli et al. in view of Williams.
Regarding claim 10, Cignoli discloses all the features with respect to claim 1 as indicated above. Cignoli does not explicitly disclose sensing circuitry having a sensor input and a sensor output, in which the sensor input of the sensing circuitry is coupled to the switch output, and the sensing circuitry is configured to provide a sense signal at the sensor output representative of current through the first switch.
However, Williams discloses [fig. 11] discloses sensing circuitry [560] having a sensor input [input to 560] and a sensor output [output 560], in which the sensor input of the sensing circuitry is coupled to the switch output, and the sensing circuitry is configured to provide a sense signal [VB] at the sensor output representative of current through the first switch. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Cignoli as taught in Williams in order to accurately sense the current in discrete semiconductor devices.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Williams.
Regarding claim 13, Williams in the embodiment of fig. 7C discloses all the features with
respect to claim 12 as indicated above. Williams (in the embodiment of fig. 7C) further discloses
wherein the control signal is a first control signal [VG₂]. Williams (in the embodiment of fig. 7C)
does not explicitly disclose a third transistor, in which the third transistor is configured to
conduct current through the third transistor between third and fourth current terminals thereof
responsive to a second control signal having a respective value, and the fourth current terminal is
coupled to the first current terminal.
However, Williams in the embodiment of [fig. 11] wherein a third transistor [556], in
which the third transistor is configured to conduct current through the third transistor between
third and fourth current terminals thereof responsive to a second control signal [VG₃] having a
respective value, and the fourth current terminal is coupled to the first current terminal. It would have been obvious to one of ordinary skill in the art before the effective filling date of the
claimed invention to modify the apparatus of Williams in the embodiment of [fig. 7C] by
incorporating third transistor as taught Williams in the embodiment of fig. 11 to accurately sense
the current in discrete semiconductor devices.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Williams in view of Cignoli et al.
Regarding claim 18, Williams disclose an integrated circuit [figs. 7C and fig. 8], comprising: a first transistor [403A] having first and second current terminals [source/drain terminal] and a first control terminal [gate terminal]; a plurality of second transistors [403B and 1051B~105 1n, fig. 17A], in which each of the second transistors has respective third and fourth current terminals [drain/source terminals] and a second control terminal [gate terminal], each second control terminal is coupled to the first control terminal, the first transistor occupies an area of the integrated circuit that is larger than each of the second transistors, and each of the second transistors is spatially distributed across the area occupied by the first transistor [see page 43, lines 19-30]; a switch network [404] coupled between the first current terminal and at least some of the third current terminals. Williams (in the embodiment of fig. 7C) does not explicitly disclose sensing circuitry having a sensor input and a sensor output, in which the fourth current terminal of at least one of the second transistors is coupled to the sensor input. However, Williams (in the embodiment of fig. 11) discloses sensing circuitry [560] having a sensor input [Vα] and a sensor output [output 560], in which the fourth current terminal of at least one of the second transistors is coupled to the sensor input. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Williams in the embodiment of [fig. 7C] by incorporating sensing circuitry as taught Williams in the embodiment of fig. 11 to accurately sense the current in semiconductor devices. Williams disclose in the embodiment of fig. 7C and fig. 7C does not explicitly disclose the switch network configurable to electrically connect the first current terminal to the at least some of the third current terminals and electrically disconnect the first current terminal from the at least some of the third current terminals.
However, Cignoli discloses [fig. 3] a switch network [S2] configurable to electrically connect [when switch S2 closes] a second current terminal [drain] of a first transistor [QLS] to a third current terminal [drain] of a second transistor [MLS] and electrically disconnect [when switch S2 open] the second current terminal of the first transistor from the third current terminal. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Williams in the embodiment of [fig. 7C and fig. 11] as taught Cignoli in order to utilize well known function of switching circuit.
Regarding claim 19, Williams in view of Cignoli discloses further comprising: a third transistor [556, fig. 11] having fifth and sixth current terminals [drain/source terminal] and a third control terminal [control terminal 556], in which the fifth current terminal is coupled to a voltage supply terminal [Vbatt], and the sixth current terminal is coupled to the first current terminal.
Allowable Subject Matter
Claims 4-9, 11, 14-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 18 have been considered but are moot because the new ground of rejection.
Applicant's arguments with respect to claim 12, filed on 01/30/2026 have been fully considered but they are not persuasive.
Regarding claim 12, applicant argues that at least the limitations of “a switch network coupled between at least one terminal of the second transistor and at least one terminal of the first transistor responsive to the control signal having a second value" of independent claim 12 are not disclosed explicitly or inherently in Williams and that Williams, thereby, fails to anticipate independent claim 12. Examiner respectfully disagrees.
The claim limitation require only that the switch network to be coupled between at least one terminal of the first transistor and at least one terminal of the second transistor, and that it be responsive to the control signal having a second value.
Figure 7C of Williams shows switch network 404 connected between transistor 403a (the first transistor) and transistor 403b (the second transistor). The figure and description make clear that the switch network 404 form an electrical coupling between terminals of the two transistors. This satisfies the structural requirement that the switch network be “couples between at least one terminal of the first transistor and at least one terminal of the second transistor”. Williams further discloses the switch network 404 alternately samples the two voltages Vα and Vβ at the terminals of transistors 403a and 403b and main MOSFET 403A, a sense MOSFET 403B whereby a digital control circuit adjusts the current ID2 from a current source 411 to ensure that Vα = Vβ. Williams figure 7C control signal VG2 necessarily assumes at least two values-one that turns the transistor on and another that turns them off. Without VG2 transitioning between these values, the circuit simply can not function as intended. The switching of transistors 403a and 403b depends directly on VG2. Because VG2 must have a “second value” to change the conduction states of the transistor, the switch network 404 is inherently responsive to VG2. Even if, 404 does not receive VG2 directly at its gate, its operation is indirectly but necessarily controlled by VG2 because 404 samples or interacts with the voltage Vα and Vβ at the terminals of 403a and 403b. Those node voltages changes only when VG2 changes. Thus, 404 behavior is a direct consequence of VG2 with the second value. Therefore, Williams still read on the claims and the rejection stands.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842