Prosecution Insights
Last updated: October 27, 2026
Application No. 18/622,913

APPARATUSES, SYSTEMS, AND METHODS FOR SCHEDULING PROCESSOR OPERATIONS

Non-Final OA §112
Filed
Mar 30, 2024
Examiner
HO, ANDY
Art Unit
2194
Tech Center
2100 — Computer Architecture & Software
Assignee
Advanced Micro Devices Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
944 granted / 1031 resolved
+36.6% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
12 currently pending
Career history
1043
Total Applications
across all art units

Statute-Specific Performance

§101
16.6%
-23.4% vs TC avg
§103
18.2%
-21.8% vs TC avg
§102
29.6%
-10.4% vs TC avg
§112
25.4%
-14.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1031 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION 1. This action is in response to the application filed 3/30/2024. 2. Claims 1-20 have been examined and are pending in the application. Claim Rejections - 35 USC § 112 The following is a quotation of the second paragraph of 35 U.S.C. 112: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 3. Claims 2-5, 7-8, 10-11, 15-16 and 20 are rejected under 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. A. The following terms lack antecedent basis: (i) delaying the broadcast of the scheduler update associated with the picked ready scheduler entry (lines 1-2 of claim 2). Correction is required. (ii) the scheduler entry (line 2 of claim 3; line 2 of claim 11; line 2 of claim 20). Correction is required. (iii) the cycle time threshold (line 1 of claim 4). Correction is required. (iv) the threshold (line 3 of claim 7; line 3 of claim 15). Correction is required. (v) the broadcast of the scheduler update associated with the picked ready scheduler entry (lines 1-2 of claim 10). Correction is required. B. The claim language in the following claims is not clearly understood: (i) As to claim 8, it is unclear “each scheduler entry” (line 1) refers to which limitation in claim 1 as many “scheduler entries” are disclosed in claim 1. Correction is required. (ii) As to claim 16, it is unclear “each scheduler entry” (line 1) refers to which limitation in claim 9 as many “scheduler entries” are disclosed in claim 9. Correction is required. Allowable Subject Matter 4. Claims 1, 6, 9, 12-14 and 17-19 are allowed. 5. Claims 2-5, 7-8, 10-11, 15-16 and 20 would be allowable if rewritten or amended to overcome the rejections set forth in this office action. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S Patent No. 10,719,355 discloses a microprocessor including a scheduler circuit to schedule instruction dispatches in out-of-order instruction execution. U.S Patent No. 9,830,187 discloses scheduler and performance control logic within a data processing system or electronic device perform cooperative operations in a closed loop manner to perform a runtime determination of an amount of execution resources to use when scheduling threads for execution. U.S Patent No. 9,160,679 discloses port empty transition scheduling. U.S Patent No. 8,566,829 discloses a distributed hierarchical scheduler with cooperative components for virtual engines operating in a multi-processor/multi-core environment. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andy Ho whose telephone number is (571) 272-3762. A voice mail service is also available for this number. The examiner can normally be reached on Monday – Friday, 8:30 am – 5:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Kevin Young can be reached on (571) 270-3180. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2100. Any response to this action should be mailed to: Commissioner for Patents P.O Box 1450 Alexandria, VA 22313-1450 Or fax to: AFTER-FINAL faxes must be signed and sent to (571) 273 - 8300. OFFICAL faxes must be signed and sent to (571) 273 - 8300. NON OFFICAL faxes should not be signed, please send to (571) 273 – 3762 /Andy Ho/ Primary Examiner Art Unit 2194
Read full office action

Prosecution Timeline

Mar 30, 2024
Application Filed
Jun 03, 2026
Response after Non-Final Action
Aug 03, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+7.6%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1031 resolved cases by this examiner. Grant probability derived from career allowance rate.

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