DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application. Claims 1-9 are withdrawn from further consideration.
Election/Restrictions
Applicant’s election without traverse of Group II: claims 10-20 in the reply filed on 03 August 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 01 April 2024 and 14 July 2025. The information therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10-14 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Livengood et al. (US 6,355,950) (hereinafter, “Livengood”).
Re: independent claim 10, Livengood discloses in figs. 2-3 an electronic device comprising: a semiconductor substrate (102) having a first surface and a second surface; a base metallization layer (116, 204) formed on the first surface of the semiconductor substrate to form a bottom surface of the electronic device; one or more circuit layers (including 104, 107) formed on the second surface of the semiconductor substrate to define a top surface of the electronic device, wherein one or more sidewalls extend between the bottom and top surfaces of the electronic device; a dielectric layer (208a, 208b, 212a, 212b) on the one or more sidewalls; and a metal layer (206, 210) on the dielectric layer (see also fig. 3).
Re: claim 11, Livengood discloses in fig. 2 the electronic device of claim 10, wherein: the one or more circuit layers includes a conductive pad (110a, 110b) on the top surface; the metal layer (210) is coupled to the conductive pad (110a) through the dielectric layer (212a, 212b); and the base metallization layer (204) and the semiconductor substrate (102) are configured to be coupled to one of a negative supply voltage (VSS) or ground and are capacitively coupled to the metal layer through the dielectric layer (col 5 ll. 34-42).
Re: claim 12, Livengood discloses in fig. 2 the electronic device of claim 10, wherein the metal layer (206, 210) and the dielectric layer (208a, 208b, 212a, 212b) extend around the one or more sidewalls to form a capacitor with one or more of the semiconductor substrate (102) or the base metallization layer (116) (col 5 ll. 34-42).
Re: claim 13, Livengood discloses in fig. 2 the electronic device of claim 12, wherein the capacitor is configured to be coupled to an input/output interface to provide a decoupling function (col 5 ll. 34-42).
Re: claim 14, Livengood discloses in fig. 2 the electronic device of claim 12, wherein the capacitor is configured to be coupled to a power supply to filter noise from a power supply signal (col 5 ll. 34-42).
Re: claim 17, Livengood discloses in fig. 2 the electronic device of claim 10, wherein the base metallization layer comprises one or more of aluminum, copper, cobalt, nickel, or tungsten (col 3 ll. 26-41).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Livengood et al. (US 6,355,950) (hereinafter, “Livengood”).
Re: claims 15, Livengood discloses in fig. 2 the electronic device of claim 10.
Livengood does not disclose expressly wherein the dielectric layer includes one or more of tantalum nitride (TaN), hafnium oxide (HfO2), aluminum oxide (Al2O3), or doped tantalum pentoxide (Ta2O5).
However, Livengood discloses wherein the dielectric layer includes a material having a higher dielectric constant than silicon dioxide (col 5 ll. 34-42). The claims materials are commonly used high dielectric constant dielectric materials, i.e. have a dielectric constant higher than that of silicon dioxide.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use one or more of the claimed materials as the dielectric layer as taught by Livengood.
Allowable Subject Matter
Claims 19-20 are allowed.
Claims 16 and 18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 19, an electronic device comprising: a semiconductor substrate including a first surface and a second surface; a base metallization layer coupled to the first surface of the semiconductor substrate to define a bottom surface of the electronic device; and one or more circuit layers formed on the second surface of the semiconductor substrate to define a top surface of the electronic device, wherein one or more sidewalls of the electronic device extend between the bottom and top surfaces of the electronic device, and wherein the one or more circuit layers including one or more metal structures forming an active circuit area and including at least one contact pad on the top surface; a dielectric layer formed on at least a portion of the base metallization layer and on the one or more sidewalls, the dielectric layer including an open area over the at least one contact pad; a metal layer on the dielectric layer over the sidewalls and coupled to the at least one contact pad; and as recited in claim 16, the electronic device of claim 10, wherein one or more of the metal layer or the dielectric layer forms an ionic-contamination barrier structure; and as recited in claim 18, the electronic device of claim 10, further including one or more scribe-lane extensions extending from the one or more sidewalls, each of the one or more scribe-lane extensions including portions of the base metallization layer, the dielectric layer, and the metal layer.
Conclusion
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 8/24/2026
Prosecution Insights