Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 07/28/2026, with respect to the rejections of claim 1, 9 and 17 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Cheng et al. ( US 2017/0372957 A1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2022/0336460 A1), in view of Cheng et al. (US 2017/0372957 A1; hereinafter “Cheng”).
In regard to claim 1, Liaw teaches a semiconductor structure (a GAA device 100) (Fig. 20B and paragraph 15), comprising: gate sidewall spacers (gate spacers 240) disposed on sidewalls of a gate structure (high-k metal gates (HKMG) 270-272 are shown with gate spacers 240 in Fig. 20B) (Fig. 20B and paragraphs 49 and 52)
Liaw doesn’t explicitly teach a column-shaped dielectric sidewall spacer disposed on sidewalls of the dielectric gate cap and on the gate structure, wherein the column-shaped dielectric sidewall spacer comprises a vertically extending portion disposed within a gate recess region arranged between the gate structure and a given one of the gate sidewall spacers and surrounds the dielectric gate cap, wherein the gate recess region has a sidewall that is coplanar with a sidewall shared between the gate structure and the given one of the gate sidewall spacers.
Cheng teaches a semiconductor structure (a semiconductor device 10) (Fig. 10 and paragraph 28), comprising:
a column-shaped dielectric sidewall spacer (dielectric layer 38 and partial caps 40) disposed on sidewalls of a dielectric gate cap (ILD layer 30) and on a gate structure (a gate structure 26) (Fig. 1, Fig. 7 and paragraphs 35, 37 and 41) , wherein the column-shaped dielectric sidewall spacer comprises a vertically extending portion disposed within a gate recess region (a recesses 36 which is column shaped due to extending vertically) arranged between the gate structure and a given one of the gate sidewall spacers (spacers 20) and surrounds the dielectric gate cap (a dielectric layer 38 is deposited to fill the recesses 36 between the spacers 20 and the gate structure 26 while also surrounding the ILD layer 30) (Fig. 5, Fig. 7 and paragraph 40), wherein the gate recess region has a sidewall that is coplanar with a sidewall shared between the gate structure and the given one of the gate sidewall spacers (the recess 36 filled by dielectric layer 38 has a side wall coplanar with a sidewall directly below it shared by gate structure 26 and spacer 20).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw in view of Cheng to have teach a column-shaped dielectric sidewall spacer disposed on sidewalls of the dielectric gate cap and on the gate structure, wherein the column-shaped dielectric sidewall spacer comprises a vertically extending portion disposed within a gate recess region arranged between the gate structure and a given one of the gate sidewall spacers and surrounds the dielectric gate cap, wherein the gate recess region has a sidewall that is coplanar with a sidewall shared between the gate structure and the given one of the gate sidewall spacers since this layout allows for the separation of electrical components within the device and preventing unwanted shorts while increasing the volume of the gate conductor as taught by Cheng (paragraphs 1-5).
Claims 2-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Cheng as applied to claim 1 above, and further in view of Xie et al. (US 2021/0082770 A1; hereinafter “Xie”)
In regard to claim 2, Liaw in view of Cheng doesn’t explicitly teach a metal gate contact disposed within the dielectric gate cap.
Xie teaches a semiconductor structure (a semiconductor structure 100) (Fig. 1A and paragraph 40), further comprising a metal gate contact (a gate contact 160c) disposed within a dielectric gate cap (the gate contact 160c is between liner layers 152) (Fig. 1A, Fig. 16B and paragraphs 73 and 77).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw in view of Cheng with the teachings of Xie to have a metal gate contact disposed within the dielectric gate cap since this layout is well known amongst those skilled in the art to increase the functionality of the device by allowing contact points with the gate structure while preventing unwanted shorts.
In regard to claim 3, Liaw in view of Cheng and Xie teaches wherein a column-shaped dielectric sidewall spacer (gate spacers 112 are considered column-shaped due to extending vertically) is disposed on lateral sides of the metal gate contact (the gate spacers 112 are shown on the side walls of the gate contact 160c in Xie Fig. 16B).
In regard to claim 4, Liaw teaches the semiconductor structure, further comprising a source/drain region (source/drain features 208 ) disposed adjacent the gate structure (the source/drain features 208 are shown adjacent to the high-k metal gates (HKMG) 270-272) (Fig. 20B and paragraph 33), and a source/drain metal contact (contact features 280) disposed on the source/drain region (Fig. 29B and paragraph 57).
In regard to claim 5, Liaw in view of Cheng doesn’t explicitly teach wherein the source/drain metal contact is lower than the metal gate contact.
Xie teaches source/drain metal contact (source/drain contact 142) is lower than the metal gate contact (the source/drain contact 142 are shown lower than the gate contact 160c in Figs. 16A and 16B) (Fig. 16A and paragraphs 69 and 76).
It would’ve obvious to one skilled in the art to combine the teachings of Liaw in view of Cheng with the teachings of Xie to have the source/drain metal contact is lower than the metal gate contact since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
In regard to claim 6, Liaw in view of Cheng and Xie teach further comprising a metal via disposed on the source/drain metal contact (a via forming source/drain contacts 160a and 160b are shown above the source/drain contact142 in Xie Fig. 16A) (Xie Fig. 16A and paragraph 76).
In regard to claim 8, Liaw in view of Cheng doesn’t explicitly teach wherein the given one of the gate sidewall spacers comprises a tapered side surface.
Xie teaches a given one of the gate sidewall spacers comprises a tapered side surface (a tapered side of gate spacers 112 is shown in Fig. 16A) (Fig. 16A and paragraph 69).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw in view of Cheng with the teachings of Xie to have the given one of the gate sidewall spacers comprise a tapered side surface since it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Cheng as applied to claim 1 above, and further in view of Chen et al. (US 2018/0337092 A1; hereinafter “Chen”)
In regard to claim 7, Liaw in view of Cheng and Xie don’t explicitly teach wherein the column-shaped dielectric sidewall spacer comprises a high-K dielectric material and the gate sidewall spacers comprise a low-k dielectric material.
Chen teaches a semiconductor structure (a semiconductor device as shown in Fig. 1A) (Fig. 1A and paragraph 10), wherein a column-shaped dielectric sidewall spacer (a side wall of protective layer 70 is considered column-shaped due to extending vertically) comprises a high-K dielectric material (aluminum oxide) and a gate sidewall spacers (sidewall spacers 20) comprise a low-k dielectric material (a sidewall spacer 30 is made of a low-k dielectric and a side wall of protective layer 70 is made of aluminum oxide which is a known high-k dielectric material) (Fig. 10 and paragraphs 13 and 28).
It would’ve been obvious to one skilled in the art to combine the teachings of Liaw in view of Cheng and Xie with the teachings of Chen to have the dielectric sidewall spacer comprises a high-K dielectric material and the gate sidewall spacers comprise a low-k dielectric material since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 9-14, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Cheng.
In regard to claim 9, Xie teaches a semiconductor structure (a semiconductor structure 100) (Fig. 1A and paragraph 40), comprising:
first gate sidewall spacers (gate spacers 112 annotated as 1st in annotated Fig. 16B below) disposed on sidewalls of a first gate structure on a first channel region (gate structures 110 annotated as 1st further include gate spacers 112 on the sidewalls of the gate structure on a channel region) (Fig. 16A and paragraph 59);
a first dielectric gate cap (ILD layer 154 over the gate structure 110 annotated as 1st) disposed over a portion of the first gate structure (the ILD layer 154 is disposed over the gate structures 110) (Fig. 16A and paragraph 74);
a column-shaped first dielectric sidewall spacer (a vertical portion of the liner layer 152 over the gate structure 110 annotated as 1st is considered column-shaped) disposed on sidewalls of the first dielectric gate cap (the liner layer 152 is shown on the sidewalls of the ILD layer 154) (Fig. 16A and paragraph 74),
second gate sidewall spacers (gate spacers 112 annotated as 2nd in annotated Fig. 16B below) disposed on sidewalls of a second gate structure on a second channel region adjacent the first channel region (gate structures 110 annotated as 2nd further include gate spacers 112 on the sidewalls of the gate structure on a channel region (Fig. 16A and paragraph 59);
a second dielectric gate cap (ILD layer 154 over the gate structure 110 annotated as 2nd) disposed over the second gate structure (the ILD layer 154 is disposed over the gate structures 110) (Fig. 16A and paragraph 74); and
a second dielectric sidewall spacer (a liner layer 152 over the gate structure 110 annotated as 2nd) disposed on sidewalls of the second dielectric gate cap and surrounds the second dielectric gate cap (the liner layer 152 is shown on the sidewalls of the ILD layer 154) (Fig. 16A and paragraph 74).
However, Xie doesn’t explicitly teach wherein the column-shaped first dielectric sidewall spacer comprises a vertically extending portion disposed within a gate recess region arranged between the first gate structure and a given one of the first gate sidewall spacers and surrounds the first dielectric gate cap, wherein the gate recess region having a sidewall that is coplanar with a sidewall shared between the first gate structure and the given one of the first gate sidewall spacers.
Cheng teaches a semiconductor structure (a semiconductor device 10) (Fig. 10 and paragraph 28), comprising:
a column-shaped first dielectric sidewall spacer (dielectric layer 38 and partial caps 40) disposed on sidewalls of a dielectric gate cap (ILD layer 30) and on a gate structure (a gate structure 26) (Fig. 1, Fig. 7 and paragraphs 35, 37 and 41) , wherein the column-shaped dielectric sidewall spacer comprises a vertically extending portion disposed within a gate recess region (a recesses 36 which is column shaped due to extending vertically) arranged between the gate structure and a given one of the gate sidewall spacers (spacers 20) and surrounds the dielectric gate cap (a dielectric layer 38 is deposited to fill the recesses 36 between the spacers 20 and the gate structure 26 while also surrounding the ILD layer 30) (Fig. 5, Fig. 7 and paragraph 40), wherein the gate recess region having a sidewall that is coplanar with a sidewall shared between the gate structure and the given one of the gate sidewall spacers (the recess 36 filled by dielectric layer 38 has a side wall coplanar with a sidewall directly below it shared by gate structure 26 and spacer 20).
PNG
media_image1.png
694
863
media_image1.png
Greyscale
It would’ve been obvious to one skilled in the art to combine the teachings of Xie in view of Cheng the column-shaped dielectric sidewall spacer comprises a vertically extending portion disposed within a gate recess region arranged between the gate structure and a given one of the gate sidewall spacers and surrounds the dielectric gate cap, wherein the gate recess region has a sidewall that is coplanar with a sidewall shared between the gate structure and the given one of the gate sidewall spacers since this layout allows for the separation of electrical components within the device and preventing unwanted shorts while increasing the volume of the gate conductor as taught by Cheng (paragraphs 1-5).
In regard to claim 10, Xie teaches further comprising a metal gate contact (a gate contact 160c) disposed within the first dielectric gate cap (the gate contact 160c is within the ILD layer 154) (Fig. 1A, Fig. 16B and paragraph 74).
In regard to claim 11, Xie teaches wherein the column-shaped first dielectric sidewall spacer is disposed on lateral sides of the metal gate contact (the gate spacer 112 is shown on side walls of the gate contact 160c) (Fig. 16B).
In regard to claim 12, Xie teaches the semiconductor structure, further comprising a source/drain region (source/drain regions 108) disposed between the first gate structure and the second gate structure (annotated Fig. 16B and paragraph 41), and a source/drain metal contact (source/drain contact 142) disposed on the source/drain region (Fig. 16A and paragraph 69).
In regard to claim 13, Xie teaches wherein the source/drain metal contact is lower than the metal gate contact (the source/drain contact 142 is lower than the gate contact 160c as shown in Figs. 16A and 16B).
In regard to claim 14, Xie teaches the semiconductor structure, further comprising a metal via (source/drain contacts 160a and 160b) disposed on the source/drain metal contact (Fig. 16A and paragraph 76).
In regard to claim 16, Xie teaches wherein the given one of the first gate sidewall spacers comprises a tapered side surface (a tapered side of gate spacers 112 is shown in Fig. 16A) (Fig. 16A and paragraph 69).
In regard to claim 17, Xie teaches an integrated circuit (an integrated circuit) (Fig. 1A and paragraph 39), comprising: one or more semiconductor structures (semiconductor structure 100) (Fig. 1A and paragraph 40), wherein at least one of the one or more semiconductor structures comprises:
gate sidewall spacers (gate spacers 112) disposed on sidewalls of a gate structure (gate structures 110 annotated include gate spacers 112 on the sidewalls) (Fig. 16A and paragraph 59);
a dielectric gate cap (ILD layer 154) disposed over a portion of the gate structure (the ILD layer 154 is disposed over the gate structures 110) (Fig. 16A and paragraph 74); and
a column-shaped dielectric sidewall spacer (a vertical portion of a liner layer 152 ) disposed on sidewalls of the dielectric gate cap and on the gate structure (the liner layer 152 is shown on the sidewalls of the ILD layer 154) (Fig. 16A and paragraph 74).
However, Xie doesn’t explicitly teach wherein the column-shaped dielectric sidewall spacer comprises a vertically extending portion disposed within a gate recess region arranged between the gate structure and a given one of the gate sidewall spacers and surrounds the dielectric gate cap, wherein the gate recess region having a sidewall that is coplanar with a sidewall shared between the gate structure and the given one of the gate sidewall spacers.
Cheng teaches an integrated circuit (integrated circuit chips) (paragraph 21), comprising: one or more semiconductor structures (present embodiments of the semiconductor device 10 may include a design for an integrated circuit chip) (paragraph 20), comprising:
a column-shaped dielectric sidewall spacer (dielectric layer 38 and partial caps 40) disposed on sidewalls of a dielectric gate cap (ILD layer 30) and on a gate structure (a gate structure 26) (Fig. 1, Fig. 7 and paragraphs 35, 37 and 41) , wherein the column-shaped dielectric sidewall spacer comprises a vertically extending portion disposed within a gate recess region (a recesses 36 which is column shaped due to extending vertically) arranged between the gate structure and a given one of the gate sidewall spacers (spacers 20) and surrounds the dielectric gate cap (a dielectric layer 38 is deposited to fill the recesses 36 between the spacers 20 and the gate structure 26 while also surrounding the ILD layer 30) (Fig. 5, Fig. 7 and paragraph 40), wherein the gate recess region having a sidewall that is coplanar with a sidewall shared between the gate structure and the given one of the gate sidewall spacers (the recess 36 filled by dielectric layer 38 has a side wall coplanar with a sidewall directly below it shared by gate structure 26 and spacer 20).
It would’ve been obvious to one skilled in the art to combine the teachings of Xie with the teachings of Cheng to have the dielectric sidewall spacer extend into a gate recess region arranged between the gate structure and a given one of the gate sidewall spacers and surround the dielectric gate cap since this allows separation of conductive regions within the device and prevent unwanted shorts as taught by Cheng (paragraph 48).
In regard to claim 18, Xie teaches wherein the at least one of the one or more semiconductor structures further comprises:
a metal gate contact (a gate contact 160c) disposed within the dielectric gate cap (the gate contact 160c is within the ILD layer 154) (Fig. 1A, Fig. 16B and paragraph 74), wherein the dielectric column-shaped sidewall spacer is disposed on lateral sides of the metal gate contact (the vertical portion of a liner layer 152 is shown on the lateral side of the gate contact 160c) (Fig. 16B); a source/drain region (source/drain regions 108) disposed adjacent the gate structure (Fig. 16B and paragraph 41); and a source/drain metal contact (source/drain contact 142) disposed on the source/drain region (Fig. 16A and paragraph 69), wherein the source/drain metal contact is lower than the metal gate contact (the source/drain contact 142 is lower than the gate contact 160c as shown in Figs. 16A and 16B).
In regard to claim 20, Xie teaches wherein the given one of the gate sidewall spacers comprises a tapered side surface (a tapered side of gate spacers 112 is shown in Fig. 16A) (Fig. 16A and paragraph 69).
Claims 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Cheng as applied to claims 9 or 17 above, and further in view of Chen.
In regard to claim 15, Xie in view of Cheng doesn’t explicitly teach wherein the first dielectric sidewall spacer and the second dielectric sidewall spacer each comprise a high-K dielectric material and the first gate sidewall spacers and the second gate sidewall spacers each comprise a low-k dielectric material.
Chen teaches a semiconductor structure (a semiconductor device as shown in Fig. 1A) (Fig. 1A and paragraph 10), wherein a column-shaped first dielectric sidewall spacer (a side wall of protective layer 70 on the left is column shaped due to having a vertically extending portion) and the second dielectric sidewall spacer (a side wall of protective layer 70 on the right) each comprise a high-K dielectric material (aluminum oxide) and a first gate sidewall spacers (sidewall spacers 20 on the left) and a second gate sidewall spacers (sidewall spacers 20 on the right) each comprise a low-k dielectric material (a sidewall spacer 30 is made of a low-k dielectric and a side wall of protective layer 70 is made of aluminum oxide which is a known high-k dielectric material) (Fig. 10 and paragraphs 13 and 28).
It would’ve been obvious to one skilled in the art to combine the teachings of Xie in view of Cheng with the teachings of Chen to have the first dielectric sidewall spacer and the second dielectric sidewall spacer each comprise a high-K dielectric material and the first gate sidewall spacers and the second gate sidewall spacers each comprise a low-k dielectric material since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 19, Xie doesn’t explicitly teach wherein the dielectric sidewall spacer comprises a high-K dielectric material and the gate sidewall spacers comprise a low-k dielectric material.
Chen teaches a semiconductor structure (a semiconductor device as shown in Fig. 1A) (Fig. 1A and paragraph 10), wherein a column-shaped dielectric sidewall spacer (a side wall of protective layer 70) comprises a high-K dielectric material (aluminum oxide) and a gate sidewall spacers (sidewall spacers 20) comprise a low-k dielectric material (a sidewall spacer 30 is made of a low-k dielectric and a side wall of protective layer 70 is made of aluminum oxide which is a known high-k dielectric material) (Fig. 10 and paragraphs 13 and 28).
It would’ve been obvious to one skilled in the art to combine the teachings of Xie in view of Cheng with the teachings of Chen to have the dielectric sidewall spacer comprises a high-K dielectric material and the gate sidewall spacers comprise a low-k dielectric material since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang et al. (US 20210305382 A1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights