DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/20/2026 has been entered.
Terminal Disclaimer 2/2/2026.
Other Refs: Porterfield (US 6069638) – Address Mapping Interface to main memory.; Venkumar (US 20140201494).
Non-patent Literature (attached) – Hao, Yuchen, Supporting Address Translation for Accelerator Centric Architectures; Published in: 2017 IEEE International Symposium on High
Performance Computer Architecture (HPCA); 2017; relevant to claimed MMY to generate a TLB entry… page addresses.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-3, 8, 9, 10, 11, 12, 13, 18, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 20150356024) and in view of Bogusz (US 20180004678) and further in view of Bridges (US 20070094475) and Venkumahanti (US 20140201494)
Claim 1. Loh discloses A processor device (eg., 0027 Fig. 1 - computing device 100; [0025] Processor 102 ), comprising a memory management unit (MMU) (eg., 0029 - memory management unit 114 ) configured to generate a translation lookaside buffer (TLB) entry in a TLB of the processor device for a first page virtual address (VA) (eg., 0032 Fig. 1 - . Each TLB 120 includes special-purpose lookup circuits that are configured to use the information based on previously acquired virtual address to physical address translations to perform virtual address to physical address translations faster than the same translations could be performed using page table 122.), wherein:
the TLB entry comprises a plurality of data portions that comprises a corresponding plurality of page physical addresses (PAs); (eg., Tag 304 includes information based on at least one virtual address that translates into a physical address in physical address 306. For example, in some embodiments, tag 304 includes address information (e.g., address bits) from a particular/single virtual address that translates into the physical address in physical address 306. ).
Loh does not disclose, but Bogusz discloses
one or more second data portions of the plurality of data portions comprise corresponding one or more page PAs of corresponding next sequential page VAs following the first page VA (e.g., physical addresses stored within an entry are the translations of virtual addresses in a predefined order, which may be a sequential order of consecutive virtual addresses., 0051 Fig. 6).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, providing the benefit of data processing activity can provide the address translation storage/circuitry with an indication of the region (of virtual addresses in a predefined order) which it is currently processing and physical address translations can then be provided from the address translation storage from a part (referred to herein as a segment) thereof identified by that indication and in which the physical address translations have previously been stored in the corresponding predefined order (see Bogusz, 0022).
Loh in view of Bogusz does not disclose, but Bridges discloses
the TLB entry comprises a tag that comprises the first page VA and none of the next seqiuential page VAs following the first page VA. (e.g., 0027 - tag fields of the TLB entries 182 with the virtual address shown in bits 0 to 11, to see whether the virtual address indicated by the tag field of any of the TLB entries 182 in the TLB 180 matches the virtual address).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, with Bridges providing the benefit of A TLB may also store information regarding one or more memory attributes, in addition to information about virtual-to-physical address translations. These memory attributes may, for example, include protection characteristics of memory entries, such as read/write/execute permissions. The memory attributes cached in a TLB may be accessed before, or in parallel with, the access to the memory cache (see Bridges, 0006).
Loh in view of Bogusz in view of Bridges does not disclose, but Venkumahanti discloses
a first data portion of the plurality of data portions comprises a page PA corresponding to the first page VA. (e.g., [0024] The TLB 130 may include one or more entries. In FIG. 1, the TLB 130 includes a first entry 131, a second entry 132, a third entry 133, and a fourth entry 134, where each of the entries 131-134 corresponds to a row of the TLB 130. Each entry 131-134 may include a virtual address ("Virt. Addr.") and a page size indication ("Page Size Ind."). the page size indication is represented using actual page sizes (e.g., 4 kilobytes (K), 64K, 1 megabyte (MB), 16 MB, etc.). [0025] The entries 131-134 of the TLB 130 may also include a physical address ("Phys. Addr.") that is mapped to the virtual address; 0026 - virtual address in the TLB 130 may represent a virtual page number rather than a specific address of a virtual page; [0027] As shown in FIG. 1, the first entry 131 corresponds to a 4K page starting at virtual address 0x10000. Thus, in terms of the 32-bit address space, the 4K page includes virtual addresses 0x10000000 to 0x10000FFF).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, with Bridges with Venkumahanti providing the benefit of To maintain data consistency, it may be useful to prevent situations in which multiple entries of the TLB match an input virtual address (0004) to perform processor-level overlap checking at a TLB, which may increase reliability and data consistency in a computing system or electronic device without relying on potentially erroneous third-party methods (0015).
Claim 2. Loh discloses wherein: the MMU is further configured to:
receive a first memory access request comprising a first VA (e.g., receives a virtual address, 0075); and
determine whether a first TLB access to the TLB for the first page VA of the first VA results in a miss (e.g., If the lookup misses in consecutive page lookup table 204, TLB 120 performs a lookup in consecutive region lookup table 206…If the lookups miss in all of the tables in the hierarchy of tables, a page table walk is performed, 0081 Fig. 8; Page table walks are known in the art, 0079;); and
the MMU is configured to generate the TLB entry responsive to determining that the first TLB access to the TLB for the first page VA of the first VA results in the miss (eg., 0081 - TLB 120 performs a lookup in consecutive page lookup table 204. If the lookup misses in consecutive page lookup table 204, TLB 120 performs a lookup in consecutive region lookup table 206. When the lookup hits in a given table (and thus a virtual address to physical address translation is found in the table), the series/sequential lookup is halted (and lookups are not performed in any remaining tables) and the physical address acquired from the table is used as the translation. If the lookups miss in all of the tables in the hierarchy of tables, a page table walk is performed such as with the parallel lookups described in FIG. 8 (i.e., steps 808-810).
Claim 3. Loh discloses wherein the TLB entry further comprises a plurality of valid bits that each correspond to a data portion of the plurality of data portions (e.g., the information about the entry 400 includes one or more of validity info, 0054 Fig. 4).
Claim 8. Loh discloses wherein the tag of the TLB entry further comprises one or more of a context and a page size (e.g., the information about the one or more pages in memory includes one or more of page permissions (read/write, execute, etc.), page replacement information, page validity information, etc. Because metadata 410 potentially applies to multiple pages (one for each page flag 408), metadata 410 may be arranged to indicate the one or more pages to which metadata 410 applies, e.g., via bitmasks in which each position represents a page and/or other indicator. In addition, metadata 410 may have different information for different pages., 0054 Fig. 4). .
Claim 9. Loh discloses wherein the plurality of data portions each further comprises one or more memory attributes (e.g., the information about the entry 400 includes one or more of validity info, timeout values, usage counts, usage timers, error correcting codes, 0054). .
Claim 10. Loh discloses integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter (e.g., Computing device 100 can be or can be included in any electronic device that performs computational operations. For example, computing device 100 can be or can be included in electronic devices such as desktop computers, laptop computers, wearable computing devices, tablet computers, smart phones, servers, network appliances, toys, audio-visual equipment, home appliances, controllers, etc., and/or combinations thereof., 0039). .
Claim 11. Loh discloses A method for exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression, comprising generating, by a memory management unit (MMU) of a processor device, a TLB entry in a TLB of the processor device for a first page VA (eg., 0027 Fig. 1 - computing device 100; [0025] Processor 102 ) (eg., 0029 - memory management unit 114; 0032 Fig. 1 - . Each TLB 120 includes special-purpose lookup circuits that are configured to use the information based on previously acquired virtual address to physical address translations to perform virtual address to physical address translations faster than the same translations could be performed using page table 122.), wherein:
the TLB entry comprises a plurality of data portions that comprises a corresponding plurality of page physical addresses (PAs); (eg., Tag 304 includes information based on at least one virtual address that translates into a physical address in physical address 306. For example, in some embodiments, tag 304 includes address information (e.g., address bits) from a particular/single virtual address that translates into the physical address in physical address 306. ).
Loh does not disclose, but Bogusz discloses
one or more second data portions of the plurality of data portions comprise corresponding one or more page PAs of corresponding next sequential page VAs following the first page VA (e.g., physical addresses stored within an entry are the translations of virtual addresses in a predefined order, which may be a sequential order of consecutive virtual addresses., 0051 Fig. 6).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, providing the benefit of data processing activity can provide the address translation storage/circuitry with an indication of the region (of virtual addresses in a predefined order) which it is currently processing and physical address translations can then be provided from the address translation storage from a part (referred to herein as a segment) thereof identified by that indication and in which the physical address translations have previously been stored in the corresponding predefined order (see Bogusz, 0022).
Loh in view of Bogusz does not disclose, but Bridges discloses
the TLB entry comprises a tag that comprises the first page VA and none of the next seqiuential page VAs following the first page VA. (e.g., 0027 - tag fields of the TLB entries 182 with the virtual address shown in bits 0 to 11, to see whether the virtual address indicated by the tag field of any of the TLB entries 182 in the TLB 180 matches the virtual address).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, with Bridges providing the benefit of A TLB may also store information regarding one or more memory attributes, in addition to information about virtual-to-physical address translations. These memory attributes may, for example, include protection characteristics of memory entries, such as read/write/execute permissions. The memory attributes cached in a TLB may be accessed before, or in parallel with, the access to the memory cache (see Bridges, 0006).
Loh in view of Bogusz in view of Bridges does not disclose, but Venkumahanti discloses
a first data portion of the plurality of data portions comprises a page PA corresponding to the first page VA (e.g., [0024] The TLB 130 may include one or more entries. In FIG. 1, the TLB 130 includes a first entry 131, a second entry 132, a third entry 133, and a fourth entry 134, where each of the entries 131-134 corresponds to a row of the TLB 130. Each entry 131-134 may include a virtual address ("Virt. Addr.") and a page size indication ("Page Size Ind."). the page size indication is represented using actual page sizes (e.g., 4 kilobytes (K), 64K, 1 megabyte (MB), 16 MB, etc.). [0025] The entries 131-134 of the TLB 130 may also include a physical address ("Phys. Addr.") that is mapped to the virtual address; 0026 - virtual address in the TLB 130 may represent a virtual page number rather than a specific address of a virtual page; [0027] As shown in FIG. 1, the first entry 131 corresponds to a 4K page starting at virtual address 0x10000. Thus, in terms of the 32-bit address space, the 4K page includes virtual addresses 0x10000000 to 0x10000FFF).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, with Bridges with Venkumahanti providing the benefit of To maintain data consistency, it may be useful to prevent situations in which multiple entries of the TLB match an input virtual address (0004) to perform processor-level overlap checking at a TLB, which may increase reliability and data consistency in a computing system or electronic device without relying on potentially erroneous third-party methods (0015).
Claim 12 is rejected for reasons similar to Claim 2 above.
Claim 13 is rejected for reasons similar to Claim 3 above.
Claim 18 is rejected for reasons similar to Claim 8 above.
Claim 19 is rejected for reasons similar to Claim 9 above.
Claim 20. Loh discloses A processor device, comprising
means for generating a translation lookaside buffer (TLB) entry in a TLB for a first page virtual address (VA), wherein: (eg., 0027 Fig. 1 - computing device 100; [0025] Processor 102 ) (eg., 0029 - memory management unit 114; 0032 Fig. 1 - . Each TLB 120 includes special-purpose lookup circuits that are configured to use the information based on previously acquired virtual address to physical address translations to perform virtual address to physical address translations faster than the same translations could be performed using page table 122.), wherein:
the TLB entry comprises a plurality of data portions that comprises a corresponding plurality of page physical addresses (PAs); (eg., Tag 304 includes information based on at least one virtual address that translates into a physical address in physical address 306. For example, in some embodiments, tag 304 includes address information (e.g., address bits) from a particular/single virtual address that translates into the physical address in physical address 306. ).
Loh does not disclose, but Bogusz discloses
one or more second data portions of the plurality of data portions comprise corresponding one or more page PAs of corresponding next sequential page VAs following the first page VA (e.g., physical addresses stored within an entry are the translations of virtual addresses in a predefined order, which may be a sequential order of consecutive virtual addresses., 0051 Fig. 6).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, providing the benefit of data processing activity can provide the address translation storage/circuitry with an indication of the region (of virtual addresses in a predefined order) which it is currently processing and physical address translations can then be provided from the address translation storage from a part (referred to herein as a segment) thereof identified by that indication and in which the physical address translations have previously been stored in the corresponding predefined order (see Bogusz, 0022).
Loh in view of Bogusz does not disclose, but Bridges discloses
the TLB entry comprises a tag that comprises the first page VA and none of the next seqiuential page VAs following the first page VA. (e.g., 0027 - tag fields of the TLB entries 182 with the virtual address shown in bits 0 to 11, to see whether the virtual address indicated by the tag field of any of the TLB entries 182 in the TLB 180 matches the virtual address).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, with Bridges providing the benefit of A TLB may also store information regarding one or more memory attributes, in addition to information about virtual-to-physical address translations. These memory attributes may, for example, include protection characteristics of memory entries, such as read/write/execute permissions. The memory attributes cached in a TLB may be accessed before, or in parallel with, the access to the memory cache (see Bridges, 0006).
Loh in view of Bogusz in view of Bridges does not disclose, but Venkumahanti discloses
a first data portion of the plurality of data portions comprises a page PA corresponding to the first page VA (e.g., [0024] The TLB 130 may include one or more entries. In FIG. 1, the TLB 130 includes a first entry 131, a second entry 132, a third entry 133, and a fourth entry 134, where each of the entries 131-134 corresponds to a row of the TLB 130. Each entry 131-134 may include a virtual address ("Virt. Addr.") and a page size indication ("Page Size Ind."). the page size indication is represented using actual page sizes (e.g., 4 kilobytes (K), 64K, 1 megabyte (MB), 16 MB, etc.). [0025] The entries 131-134 of the TLB 130 may also include a physical address ("Phys. Addr.") that is mapped to the virtual address; 0026 - virtual address in the TLB 130 may represent a virtual page number rather than a specific address of a virtual page; [0027] As shown in FIG. 1, the first entry 131 corresponds to a 4K page starting at virtual address 0x10000. Thus, in terms of the 32-bit address space, the 4K page includes virtual addresses 0x10000000 to 0x10000FFF).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, with Bridges with Venkumahanti providing the benefit of To maintain data consistency, it may be useful to prevent situations in which multiple entries of the TLB match an input virtual address (0004) to perform processor-level overlap checking at a TLB, which may increase reliability and data consistency in a computing system or electronic device without relying on potentially erroneous third-party methods (0015).
7. Claims 4, 5, 14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 20150356024) and in view of Bogusz (cited above) and Bridges (cited above) and Venkumahanti (US 20140201494) and further in view of Podaima (US 20160306746)
Claim 4. Loh discloses the plurality of page PAs are contiguous in a system memory (e.g., physical addresses for contiguous pages in the regions., 0020 Fig. 4).
the MMU is configured (e.g., memory management unit 114 , 0075, Fig. 1);
perform an address translation operation to obtain the page PA corresponding to the first page VA (e.g., memory management unit 114 performs a page table walk (in page table 122) to acquire the physical address (step 808). page table walk comprises checking virtual address to physical address translations in page table 122 until a virtual address to physical address translation is found for the virtual address., 0079);
store the page PA in the first data portion of the TLB entry (e.g., based on the physical address acquired during the page table walk, memory management unit 114 updates, 0080);
obtain the one or more page PAs of the corresponding next sequential page VAs based on the address translation operation (e.g.,, for consecutive region lookup table 206, memory management unit 114 can determine if the physical address acquired for the virtual address is included in a page that is contiguous with other pages for contiguous virtual addresses in a 128 kB region, and if the pages in the 128 kB region are similarly contiguous,, 0080); and
Loh does not disclose, but Bogusz discloses
store the one or more page PAs of the corresponding next sequential page VAs in the one or more second data portions of the TLB entry (e.g., physical addresses stored within an entry are the translations of virtual addresses in a predefined order, which may be a sequential order of consecutive virtual addresses., 0051 Fig. 6).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, providing the benefit of data processing activity can provide the address translation storage/circuitry with an indication of the region (of virtual addresses in a predefined order) which it is currently processing and physical address translations can then be provided from the address translation storage from a part (referred to herein as a segment) thereof identified by that indication and in which the physical address translations have previously been stored in the corresponding predefined order (see Bogusz, 0022).
Loh in view of Bogusz and Bridges and Venkumahanti does not disclose, but Podaima discloses
wherein: each page PA of the plurality of page PAs comprises one of a PA and an intermediate physical address (IPA)(e.g., FIG. 8 shows a high level mapping diagram 800 of a portion of a two-stage translation, comprising a first stage translation 802, from the VA space to an Intermediate Physical Address (IPA) space, and a second stage translation 804 from the IPA space to the PA space., 0065); and
to generate the TLB entry for the first page VA by being configured to: (e.g., apply operations of creation of a new burst TLB entry., 0064 Fig. 7).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, and Bridges and Venkumahanti with Podaim, providing the benefit of a burst-TLB that can provide improved area efficiency, and scalability, while retaining the qualities of a fully-associative TLBs having fast TLB lookup (see Podaima, 0009).
Claim 5. Loh discloses
the plurality of page PAs are not contiguous in a system memory (e.g., four PA blocks are not necessarily contiguous, 0047 Fig. 3); and
the MMU is configured to by being configured to: (e.g., memory management unit 114 , 0075, Fig. 1);
perform an address translation operation to obtain the page PA corresponding to the first page VA; (e.g., memory management unit 114 performs a page table walk (in page table 122) to acquire the physical address (step 808). The page table walk comprises checking virtual address to physical address translations in page table 122 until a virtual address to physical address translation is found for the virtual address., 0079);
store the page PA in the first data portion of the TLB entry (e.g., based on the physical address acquired during the page table walk, memory management unit 114 updates, 0080).
Loh does not disclose, but Bogusz discloses
update the one or more second data portions of the TLB entry with the one or more page PAs of the corresponding next sequential page VAs (e.g., physical addresses stored within an entry are the translations of virtual addresses in a predefined order, which may be a sequential order of consecutive virtual addresses., 0051 Fig. 6).
prefetch an address translation for each of the next sequential page VAs to obtain the one or more page PAs of the corresponding next sequential page VAs (e.g., performs a prefetch operation to prefetch from memory the physical address information , 0043 Fig. 2).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, providing the benefit of data processing activity can provide the address translation storage/circuitry with an indication of the region (of virtual addresses in a predefined order) which it is currently processing and physical address translations can then be provided from the address translation storage from a part (referred to herein as a segment) thereof identified by that indication and in which the physical address translations have previously been stored in the corresponding predefined order (see Bogusz, 0022).
Loh in view of Bogusz and Bridges and Venkumahanti does not disclose, but Podaima discloses
wherein: each page PA of the plurality of page PAs comprises one of a PA and an intermediate physical address (IPA) (e.g., FIG. 8 shows a high level mapping diagram 800 of a portion of a two-stage translation, comprising a first stage translation 802, from the VA space to an Intermediate Physical Address (IPA) space, and a second stage translation 804 from the IPA space to the PA space., 0065);
and
to generate the TLB entry for the first page VA by being configured to: (e.g., apply operations of creation of a new burst TLB entry., 0064 Fig. 7).
store the page PA in the first data portion of the TLB entry (eg., Fig. 8 0065 - , from the VA space to an Intermediate Physical Address (IPA) space, and a second stage translation 804 from the IPA space to the PA space.);
for each of the next sequential page VAs to obtain the one or more page PAs of the corresponding next sequential page Vas (e.g., a burst TLB tag buffer 606 can hold, associated with each burst TLB data set 604, a burst TLB tag, for example, first burst TLB tag 608-1, second burst TLB tag 608-2 . . . and S.sup.th burst TLB tag 608-S, 0054 Fig. 6);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, and Bridges and Venkumahanti and Podaim, providing the benefit of a burst-TLB that can provide improved area efficiency, and scalability, while retaining the qualities of a fully-associative TLBs having fast TLB lookup (see Podaima, 0009).
Claim 14 is rejected for reasons similar to Claim 4 above.
Claim 15 is rejected for reasons similar to Claim 5 above.
8. Claims 6, 7, 16, 17are rejected under 35 U.S.C. 103 as being unpatentable over Loh (US 20150356024) and in view of Bogusz (cited above), Bridges (cited above), and Venkumahanti (US 20140201494) Podaima (US 20160306746) and further in view of Abhishek (US 20190188149)
Claim 6. Loh discloses wherein the MMU is further configured to: (e.g., memory management unit 114 , 0075, Fig. 1).
Loh in view of Bogusz and Bridges and Venkumahanti does not disclose, but Podaima discloses
receive a second memory access request comprising the first VA (e.g., When the CPU generates a virtual address, the TLB uses the VA tag bits to search the tag bits in the N entries. If there is a match, the TLB identifies a hit , 0004);
determine that a second TLB access to the TLB for the first page VA of the first VA results in a hit (e.g., If there is a match, the TLB identifies a hit and outputs the physical page number from the matching entry., 0004);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with and Bogusz and Bridges Podaim, providing the benefit of a burst-TLB that can provide improved area efficiency, and scalability, while retaining the qualities of a fully-associative TLBs having fast TLB lookup (see Podaima, 0009).
Loh in view of Bogusz and Bridges and Venkumahanti and Podaima does not disclose, but Abhishek discloses
responsive to determining that the second TLB access to the TLB for the first page VA of the first VA results in the hit, perform a memory access operation using the page PA of the first data portion of the plurality of data portions of the TLB entry (e.g., in the event of a hit a response to that access request can be provided using the address translation data within the address translation cache, 0022);
receive a third memory access request comprising a second VA; determine that a second page VA of the second VA corresponds to a next sequential page VA following the first page VA (e.g., A virtual address 50 can be considered to comprise a number of bits 55 identifying a virtual page number, and some other bits 60 identifying a page offset. , 0058 Fig. 2); and
responsive to determining that the second page VA of the second VA corresponds to the next sequential page VA following the first page VA, perform a subsequent memory access operation using the page PA of a second data portion of the one or more second data portions corresponding to the next sequential page VA (e.g., address translation operation performed by the address translation circuitry 20 is illustrated schematically by the element 65 shown in FIG. 2, and serves to obtain address translation information sufficient to enable the virtual page number bits 55 to be translated into equivalent bits 70 of a physical address 80 identifying a physical page number. The page offset bits are not altered, and accordingly the page offset bits 75 are directly determined from the page offset bit 60 in the virtual address., 0058 Fig. 2; produce candidate coalesced address translation data for any number of contiguous pages, and upon a trigger condition that information collated within the buffer 38 of the prefetch circuitry 36 can then be used to derive coalesced address translation data to be stored within the address translation cache, 0066 Fig. 4).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, and Bridges, and Venkumahanti, Podaim, with Abhishek, providing the benefit of determining of address translation data to be stored within an address translation cache (see Abhishek, 0001) It would hence be desirable to provide an improved mechanism for allowing more efficient utilisation of entries in the address translation cache (0003).
Claim 7. Loh discloses wherein the MMU is further configured to: (e.g., memory management unit 114 , 0075, Fig. 1).
Loh in view of Bogusz and Bridges and Venkumahanti and does not disclose, but Abhishek discloses
receive a third memory access request comprising a second VA; determine that a second page VA of the second VA corresponds to a next sequential page VA following the first page VA (e.g., A virtual address 50 can be considered to comprise a number of bits 55 identifying a virtual page number, and some other bits 60 identifying a page offset. , 0058 Fig. 2); and
determine that a second page VA of the second VA corresponds to a next sequential page VA following the first page VA; responsive to determining that the second page VA of the second VA corresponds to the next sequential page VA following the first page VA, perform a subsequent memory access operation using the page PA of a second data portion of the one or more second data portions corresponding to the next sequential page VA (e.g., address translation operation performed by the address translation circuitry 20 is illustrated schematically by the element 65 shown in FIG. 2, and serves to obtain address translation information sufficient to enable the virtual page number bits 55 to be translated into equivalent bits 70 of a physical address 80 identifying a physical page number. The page offset bits are not altered, and accordingly the page offset bits 75 are directly determined from the page offset bit 60 in the virtual address., 0058 Fig. 2; produce candidate coalesced address translation data for any number of contiguous pages, and upon a trigger condition that information collated within the buffer 38 of the prefetch circuitry 36 can then be used to derive coalesced address translation data to be stored within the address translation cache, 0066 Fig. 4).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, and Bogusz and Bridges and Venkumahanti with Abhishek, providing the benefit of determining of address translation data to be stored within an address translation cache (see Abhishek, 0001) It would hence be desirable to provide an improved mechanism for allowing more efficient utilisation of entries in the address translation cache (0003).
Claim 16 is rejected for reasons similar to Claim 6 above.
Claim 17 is rejected for reasons similar to Claim 7 above.
Response to Arguments
Applicant's arguments filed 5/20/2026 have been fully considered but they are not persuasive.
For claims 1, 11 and 20, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Loh in view of Bogusz in view of Bridges does not disclose, but Venkumahanti discloses
a first data portion of the plurality of data portions comprises a page PA corresponding to the first page VA (e.g., [0024] The TLB 130 may include one or more entries. In FIG. 1, the TLB 130 includes a first entry 131, a second entry 132, a third entry 133, and a fourth entry 134, where each of the entries 131-134 corresponds to a row of the TLB 130. Each entry 131-134 may include a virtual address ("Virt. Addr.") and a page size indication ("Page Size Ind."). the page size indication is represented using actual page sizes (e.g., 4 kilobytes (K), 64K, 1 megabyte (MB), 16 MB, etc.). [0025] The entries 131-134 of the TLB 130 may also include a physical address ("Phys. Addr.") that is mapped to the virtual address; 0026 - virtual address in the TLB 130 may represent a virtual page number rather than a specific address of a virtual page; [0027] As shown in FIG. 1, the first entry 131 corresponds to a 4K page starting at virtual address 0x10000. Thus, in terms of the 32-bit address space, the 4K page includes virtual addresses 0x10000000 to 0x10000FFF).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the TLB and MMU for creating new entries when miss as disclosed by Loh, with Bogusz, with Bridges with Venkumahanti providing the benefit of To maintain data consistency, it may be useful to prevent situations in which multiple entries of the TLB match an input virtual address (0004) to perform processor-level overlap checking at a TLB, which may increase reliability and data consistency in a computing system or electronic device without relying on potentially erroneous third-party methods (0015).
Applicant’s arguments for dependent claims are based on their respective base independent claims 1, 11 and 20, which are addressed above.
Conclusion
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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