DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3, 5-13 and 15-21 are pending, claims 2, 4 and 14 are canceled, and claims 1, 5, 6, 12 and 15 are amended.
Response to Arguments
With respect to rejection of claims under 35 U.S.C. 101, applicant asserts “claims 1 and 12 have been amended to recite the subject matter of claim 4. Therefore, reconsideration and withdrawal of this rejection is respectfully requested”. In response, examiner respectfully submits that upon further consideration the added limitation of claim 4 into the claim 1 does not overcome the rejection of the claim under 35 U.S.C. 101. Because the limitation of “the serial data link is a controller area network (CAN) protocol and wherein the plurality of electronic control modules are configured to comply with the CAN protocol” is recited at a high level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an invention concept.
Applicant arguments with respect to rejection of claims under 35 Use 103 have been fully considered but are moot in view of a new ground of rejection.
Claim Rejections - 35 USC § 101
835 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3 and 13 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
The claims when analyzed under 2019 Revised Patent Subject Matter Eligibility Guidance, are directed to abstract idea. Claim 1 for example, recites a system, therefore, it passes the step 1 of 2019 Revised Patent Subject Matter Eligibility Guidance. The claim recites the limitation of “…receive at least a portion of a serial message…identify the serial message …as malicious based on the received portion…and in response to identifying the serial message as malicious, inject a dominate bit into the serial message to cause an error frame in the serial message… where at least six bits are injected immediately following the CAN identifier and prior to payload…”. These limitations, under broadest reasonable interpretation are directed performance of the limitation in a human mind. That is, nothing in the claim element precludes the step from practically being performed in the mind. For example, the claim encompasses a human simply receiving a portion of serial message for example on a piece of paper and identifying that the serial message is abnormal/malicious and modifying the message by inserting/writing 6 bits (dominant bit) after identifier into the message. Thus, the claim recites a mental process when analyzed under step 2A prong 1.
Claim is further analyzed in step 2A prong 2, to evaluate whether the claim as a whole integrates the recited judicial exception into a practical application of the exception. This evaluation is performed by identifying whether there are any additional elements recited in the claim beyond the judicial exception, and evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. However, each of the remaining limitation (Electronic Control module, CAN protocol) appears to be generic computer functions which do not constitute meaningful limitations that would amount to significantly more than the abstract idea. The combination of these additional element is no more than generic computer functions. Thus, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limitations on practicing the abstract idea.
Claim is additionally analyzed under Step 2B to evaluates whether the claim as a whole amount to significantly more than the recited exception, whether any additional element, or combination of additional elements, adds an inventive concept to the claim. When claims evaluated under step 2B, it is no more than what is well-understood, routine, conventional activity in the field. The specification does not provide any indication anything other than a generic computer component. The mere receiving a data element… receive at least a portion of a serial message…identify the serial message …as malicious…and in response to identifying the serial message as malicious, inject a dominate bit into the serial message to cause an error frame in the serial message…is a well-understood, routing and conventional function when it is claimed in a merely generic manner as it is here.
Independent claims 12 include limitations similar to the limitations of claim and is rejected under 35 U.S.C. 101 as being directed to abstract idea for the same reasons discussed above with respect to claim 1.
Dependent claims 2 and 3 and 13 do not cure the deficiency of the independent claims and are directed to abstract idea when analyzed under 2019 Revised Patent Subject Matter Eligibility Guidance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 6 and 12, 13, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng et al. (US Publication No. 2019/0104149), hereinafter Zeng, in view of Wesie et al. (US Publication No. 2016/0366178), hereinafter Wesie, further in view of Elend et al. (US Publication No. 2017/0093659), hereinafter Elend.
As per claim 1 and 12, Zeng discloses a system for detecting and preventing, in real time, malicious broadcasting messages from an electronic control module attempting to attack a vehicle network (paragraph [0001], “prevent an attacker from sending malicious messages…”), the system comprising: a plurality of electronic control modules in communication via a serial data link of the vehicle network (paragraph [0039], nodes are connected to each other through a bus. A plurality of ECUs, or nodes are connected to the CAN serial bus 10 ), wherein the serial data link is a controller area network (CAN) protocol and wherein the plurality of electronic control modules are configured to comply with the CAN protocol (paragraph [0039], CAN is a multi-master serial bus standard for connecting ECUs, also known as modes . A plurality of ECUs are connected to the CAN bus 10. The bus standard allows the ECUS to communicate with each other), at least a first electronic control module of the plurality of electronic control modules configured to: receive at least a portion of a serial message on the vehicle network transmitted by a second electronic control module of the plurality of electronic control modules (paragraph [0095], “when a message on a CAN bus is received, a further test is made in decision block 1304 to validate the received message”); identify the serial message from the second electronic control module as malicious based on the received portion of the serial message (paragraph [0095], “…If on the other hand, the validation fails, the SECU corrupts the message…By corrupting the message, the intended receiver(s) will ignore the message and an attacker will be unsuccessful in inflicting damage to the system”); and in response to identifying the serial message as malicious, inject a dominant bit into the serial message for the vehicle network to cause an error frame in the serial message transmitted by the second electronic control module (paragraph [0095], if validation fails message is corrupted, paragraph [0068], “writing dominate bits over the recessive bits causes the end-of frame to be corrupted. The interrupted message is thus treated as a corrupted message and ignored by all ECUs”).
While Zang discloses injecting a dominant bits into serial message in response to identifying the serial message as malicious, Zang does not explicitly disclose inject at least six dominant bits, wherein the at least six bits are injected immediately following the CAN identifier and prior to payload of the serial message. However, in an analogous art, Wesie discloses injecting at least six dominant bits (paragraph [0054]), “modifying the message, if the message is determined as illegitimate, as an error message (906). In one embodiment, six consecutive dominant bits are injected into the message”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Zang with Wesie. This would have been obvious because one of ordinary skill in the art would have been motivated to allow nodes to recognize and drop malicious messages.
While Zang in view of Wesie discloses, inject at least six dominant bits, Zang in view of Wesie does not explicitly disclose, wherein the at least six bits are injected immediately following the CAN identifier and prior to payload of the serial message. However, firstly, it is noted that the limitation of at least six bits are injected immediately following the CAN identifier and prior to payload of the serial message is considered as an obvious matter of design choice that does not patentably distinguish the claimed invention from the prior art. Wesie teaches detecting a malicious CAN message and injecting six dominate bits to invalidate the message. Wesie teaches bit level inject to disrupt an in-progress CAN message during transmission of the message stream. Accordingly, selecting the injection to occur after the identifier and before the payload represents a predictable implementation detail that does not change the function or result of message invalidation. Therefore the limitation is an obvious design choice and is not patentably significant.
Additionally, Elden discloses, injecting an error including dominant bits immediately after identifier (paragraph [0065], A CAN message can be invalidated with an error flag immediately after the identifier has been sent, or at any time later but before the EOF ends”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Zang and Wesie with Elend. This would have been obvious because one of ordinary skill in the art would have been motivated to do so in order to achieve the predictable result of preventing the malicious CAN message from being successfully and completely received by any CAN nodes on the CAN bus.
As per claim 3, Zeng furthermore discloses, wherein the dominant bit has a value of zero (paragraph [0042], “Data frames consist of one dominate 0 bit”).
As per claim 5 and 15, Zeng furthermore discloses, wherein: the serial message on the vehicle network transmitted by the second electronic control module is a first CAN message; and the first electronic control module is configured to receive a portion of a plurality of [second] CAN messages on the vehicle network transmitted by the second electronic control module (paragraph [0095], “when a message on a CAN bus is received, a further test is made in decision block 1304 to validate the received message”), identify each of the [second] CAN messages from the second electronic control module as malicious based on the received portion of each second CAN message (paragraph [0095], “…If on the other hand, the validation fails, the SECU corrupts the message…By corrupting the message, the intended receiver(s) will ignore the message and an attacker will be unsuccessful in inflicting damage to the system”), and in response to identifying the CAN message as malicious, inject a dominant bit into each [second] CAN message for the vehicle network to cause an error frame in each second CAN message transmitted by the second electronic control module and force the second electronic control module into a bus-off state (paragraph [0090], “Once the counter exceeds 255, after only thirty-two messages, the ECU is turned to the Bus Off state, disallowing it from further CAN bus communication until after 128 occurrences of 11 consecutive ‘recessive’ bits (approximately 128 messages) occur on the bus”).
Although Zeng as modified does not explicitly disclose second CAN messages, the process for receiving messages, identifying messages as malicious and injecting a dominate bit into messages does not depend on whether the message is first or second. Such processes would have been performed the same regardless of the number of the message or messages being first or second. As discussed previously Zeng discloses identifying malicious messages and injecting dominate bits into messages. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, that Zeng is capable to perform the same process on any number (i.e., second, third, Etc.) of messages, in order to achieve the predictable result of protecting the network by detecting malicious messages on all messages entering the network.
As per claim 6, Zang furthermore discloses, the first electronic control module includes a microcontroller unit (MCU) with an integrated CAN controller, and a CAN transceiver (paragraph [0040], microcontroller, CAN controller and transceiver); and the MCU is configured to inject, via the CAN transceiver, the dominant bit into the serial message for the vehicle network, thereby bypassing the integrated CAN controller (paragraph [0068], writing dominate bit).
As per claim 13, Zeng furthermore discloses wherein identifying the serial message from the second electronic control module as malicious based on the received portion of the serial message include identify the serial message from the second electronic control module as malicious based on a unique message identifier (ID) of the serial message (paragraph [0095], “validate the received message using the MAC in the message”).
As per claim 16, Zang furthermore discloses, the first electronic control module includes a microcontroller unit (MCU) with an integrated CAN controller, and a CAN transceiver (paragraph [0040], microcontroller, CAN controller and transceiver); and the MCU is configured to inject, via the CAN transceiver, the dominant bit into the serial message for the vehicle network, thereby bypassing the integrated CAN controller (paragraph [0068], writing dominate bit).
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng, Wesie and Elend, further in view of Weigand et al. (US Publication No. 2023/0237206), hereinafter Weigand.
As per claim 7 and 17, Zang furthermore discloses, wherein the MCU is configured to trigger an interrupt at a start of frame field of the serial message indicated by a bit transition from a recessive bit to a dominant bit during the start of frame field, (paragraph [0068]-[0069], “Interruption of malicious messages is conducted by the SECU, which sends high voltage through the CAN high line when an invalid MAC is detected. In the CAN protocol, high voltage in the CAN high line represents dominant bits. Since the end-of-frame for all messages must consist solely of recessive bits, writing dominant bits over the recessive bits…”).
Zeng as modified does not explicitly disclose, but in an analogous art, Weigand discloses trigger a subsequent main timer interrupt to synchronize the MCU of the first electronic control module with the second electronic control module (paragraph [0033], all of the ECUs in the CAN bus system 100 are synchronized).
It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to combine the modified Zeng and Weigand. This would have been obvious because one of ordinary skill in the art would have been motivated to allow simultaneous sampling of data on the network.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng, Wesie, Elend and Weigand, further in view of Rauber et al. (US Publication No. 2023/0237206), hereinafter Rauber.
As per claim 8 and 18, Zeng as modified does not explicitly disclose wherein the MCU is configured to trigger the subsequent main timer interrupt at seventy percent of the nominal bit time of the serial message. However, in an analogous art Rauber discloses trigger the subsequent main timer interrupt at [seventy percent] of the nominal bit time of the serial message (abstract, “data signal a bit is transmitted in the form of a signal edge generated at a particular nominal time, after triggering by an interrupt signal”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the modified Zeng with Rauber. This would have been obvious because one of ordinary skill in the art would have been motivated to do so, in order to achieve the predictable result of improving efficiency and resource utilization.
Although Rauber does not explicitly disclose interrupt at seventy percent on the nominal bit time, it is noted that it would have been obvious to one of ordinary skill in the art to trigger…main timer interrupt at any percent (i.e., 70 percent), in order to achieve the predictable result allowing customization for improving efficiency and resource utilization.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng, Wesie and Elend, further in view of Mutter et al. (US Publication No. 2020/0057745), hereinafter Mutter.
As per claim 9 and 19, Zang discloses wherein the MCU is configured to, in response to identifying the serial message as malicious, inject the dominant bit into the serial message to overwrite a recessive [stuff] bit of the serial message to cause the error frame in the serial message transmitted by the second electronic control module (paragraph [0095], if validation fails message is corrupted, paragraph [0068], “writing dominate bits over the recessive bits causes the end-of frame to be corrupted. The interrupted message is thus treated as a corrupted message and ignored by all ECUs”).
Zang as modified does not explicitly disclose, but in an analogous art, Mutter discloses overwrite a recessive stuff bit (paragraph [0098], “at least one recessive stuff bit occurs…and can then be overwritten”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the modified Zeng with Mutter. This would have been obvious because one of ordinary skill in the art would have been motivated to transfer a message in a serial bus system which operates with high data rate and excellent error robustness.
As per claim 10 and 20, Zang discloses the serial message includes a CAN ID field (paragraph [0042]); and the MCU is configured to, in response to identifying the serial message as malicious, inject the dominant bit into the serial message to overwrite the recessive stuff bit of the serial message module [after the CAN ID field]. (paragraph [0095], if validation fails message is corrupted, paragraph [0068], “writing dominate bits over the recessive bits causes the end-of frame to be corrupted. The interrupted message is thus treated as a corrupted message and ignored by all ECUs”). Mutter discloses overwrite the recessive stuff bit of the serial message module (paragraph [0098], “at least one recessive stuff bit occurs…and can then be overwritten”). Although Mutter does not explicitly disclose overwrite the recessive stuff bit is after the CAN ID field, overwaiting recessive stuff bit after the CAN ID does not include an inventive concept and it would have been obvious to one of ordinary skill in the art. One of ordinary skill in the art would have been motivated to overwrite the recessive stuff bit after the CAN ID field, in order to customize the serial messages.
Claims 11 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Zeng, Wesie, Elend, and Mutter, further in view of Jefferies et al. (US Publication No. 2013/0317693), hereinafter Jefferies.
As per claim 11 and 21, Zeng discloses, wherein the MCU is configured to, in response to identifying the serial message as malicious, [enable pin multiplexing] to inject the dominant bit into the serial message to overwrite the recessive [stuff] bit of the serial message (paragraph [0095], if validation fails message is corrupted, paragraph [0068], “writing dominate bits over the recessive bits causes the end-of frame to be corrupted. The interrupted message is thus treated as a corrupted message and ignored by all ECUs”). Mutter discloses overwrite the recessive stuff bit of the serial message module (paragraph [0098], “at least one recessive stuff bit occurs…and can then be overwritten”). The motivation is similar to the motivation provided in claim 1.
Zeng as modified does not explicitly disclose enabling pin multiplexing and disable the pin multiplexing after the dominant bit is injected into the serial message. However, the technique for enabling or disabling pin multiplexing is well known in the art as illustrated by Jefferies (paragraph [0090], the microcontroller would activate the appropriate channel (via channel select pins 575) via a digital multiplexer 576 to enable the appropriate CAN transceiver (transceivers 577, 578, 579 that can be enabled/disabled by the 1 to 3 MUX 576)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the modified Zeng with Jefferies. This would have been obvious because one of ordinary skill in the art would have been motivated to do so, in order to eliminate manual configuration.
References Cited, Not Used
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Meier (US Patent No. 11,146,420) discloses, an extension of the existing CAN FD data transmission protocol. The extension enables the use of the IPv6 protocol for the CAN bus. The CAN FD protocol is further developed in an incompatible way. One modification measure relates to the lengthening of the Data Field, which is positioned in the transmission frame after an Arbitration Field. An arbitrary number of bytes can be entered in the extended Data Field within a specified upper limit. Since the Data Field is transmitted at a higher bit rate field than the Arbitration Field, the data throughput is increased dramatically.
Olson et al. (US Publication No.2019/0129778) discloses, a technique includes monitoring a sequence of bits of data communicated to a transmitter of a node, where the transmitter communicates signals with a bus in response to the sequence of bits. The technique includes determining whether the sequence of bits represents acknowledgement by the node that data was received from the bus in an associated data frame and represents detection by the node of an error associated with the data frame. The technique includes detecting a fault associated with the bus based on the result of the determination.
Juliato et al. (US Publication No.2019/0260772) discloses, various systems and methods for bus-off attack detection. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ali Abyaneh whose telephone number is (571) 272-7961. The examiner can normally be reached on Monday-Friday from (8:00-5:00).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Lagor can be reached on (571) 270-5143. The fax phone numbers for the organization where this application or proceeding is assigned as (571) 273-8300.
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/ALI S ABYANEH/Primary Examiner, Art Unit 2437
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