DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kabushiki et al, EP 2735314, in view of Grose et al, US Patent No. 7,283,343.
Regarding claim 1, Kabushiki et al disclose a switch driving circuit, an inverter apparatus, and a power steering apparatus comprising: an electrical power system including a DC power supply in the form of a battery 4; and inverter circuit 1; the battery 4 has a positive terminal connected through a switch circuit 5 to the positive DC bus of the inverter circuit 1 and a negative terminal connected ; to the negative DC bus ( page 2; par. 004); the switch circuit 5 includes two N-channel MOSFETs 6a and 6b connected through a common source, with the drain of the MOSFET 6a connected to the positive terminal of the battery 4 and the drain of the MOSFET 6b connected to the positive DC bus inverter circuit (page 2; par. 005); the switch circuit 5 correspond to the claimed battery disconnect switching structure between a DC source connection and downstream electrical circuitry; if a reversed polarity occurs cause the switch 5 to turn on and current flow, including trough the body diodes of the inverter MOSFETs, producing destructive short circuit (page 2-3; par. 008-0010; employing semiconductor switching element 10 and 11 with respective protection diodes 13, 14 connected in parallel (page 3; par. 0012; providing current blocking diode 39 for preventing current from flowing toward switch 5 when the battery 4 is connected with reverse polarity (page 3; par. 0012); the diode 39 in inserted between the switch driving circuit 38 and the circuit ground so that overcurrent is prevented when the battery 4 is reversely connected; the switch circuit 5 comprises two oppositely connected N-channel MOSFETs 6a and 6b and the diode 39 prevent current flowing from the reference point toward the switch circuit 5 under reversed polarity (page 4; par. 0020-0022).
Kabushiki et al fail to disclose that the semiconductor component connected across the input provides a first diode branch and a second controllable switch branch operating as the claimed reversed current bypass.
Grose et al disclose an integrated reverse battery protection circuit for an external MOSFET switch comprising providing reverse conditions where if the external FET is not turned on current flows through the load and forward biases the FET back gate diode, causing substantial power dissipation (col. 3, line 49 to col. 4); providing a protection circuit that turns the external FET 165 on during the reverse battery condition to render the current path less resistive and dissipates lest energy (col. 5, line 14+); such arrangement minimizes power consumption associated with the forward biased body diode; it provides a reverse battery current path and shunt the load 170 with inherent drain to source resistance of external FET 165, approximately a 60-75% reduction in dissipated power, depending upon how the FET is turned on (Cl. 5, line 14+).
It would have been obvious to a person of ordinary skill in the art before the applicant’s effective filing date of the claimed invention to modify the reverse polarity protection arrangement of Kabushiki et al using the teachings of providing an activated semiconductor condition path associated with a diode conduction path for reducing the semiconductor power dissipation while maintaining protection of the disconnect circuitry. Therefore, it would have been an obvious extension as taught by the prior art.
Regarding claim 2, Grose et al further disclose that the protection circuit is responsive to the reverse battery condition and change the semiconductor when that condition exists; during normal operation MP1 is off, during reverse battery MP1 is on, which causes external FET 165 to turn on (col. 4, line 57 to col. 5, line 28).
It would have been obvious to implement the reverse polarity responsive circuitry of the combined system as a detection circuit because recognition of the reverse polarity electrical state is inherent in or necessary to condition responsive switching. Therefore, it would have been an obvious extension as taught by the prior art.
Regarding claim 3, Kabushiki et al further disclose an MCU and drive circuit controlling semiconductor switches; the MCU provides drive signals through half bridge drive circuit 12 to MOSFETs 10 and 11 and thereby control switch circuit 5 (see page 2, par. 0006-0007) and provides drive signals and ON/OFF command to switch circuit 5 (page 3-4; par. 0017-0019).
It would have been obvious to use the known MCU controlled gate driving architecture to implement the reverse polarity responsive switching taught by Grose et al. Therefore, it would have been an obvious extension as taught by the prior art.
Regarding claim 4, Kabushiki et al further disclose identifying drive circuit 8, such as a micro control unit (page 2, par. 0006) and identifies the MCU 35 for controlling the semiconductor circuit (page 3, par. 0017). Therefore, Kabushiki et al in view of Grose et al render the claim obvious.
Regarding claim 5, Kabushiki et al disclose that the detection circuit Fig. 2, par. 0016) that is controlled by the microprocessor (MCU 35) and does not make up a quiescent current. Therefore, Kabushiki et al in view of Grose et al render the claim obvious.
Regarding claim 6, with respect to the specific type of battery storage, such limitations is just merely an engineering choice for meeting specific customer requirement. Therefore, it would have been obvious to select the specific type of battery storage, including a low-voltage battery storage device having a nominal voltage of 12 to 60 volts. Therefore, Kabushiki et al in view of Grose et al render the claim obvious.
Regarding claim 7, Kabushiki et al disclose N-channel MOSFET semiconductor switching element and expressly identify the inverter device as power MOSFETs (page 2, par. 0004-0006). And Grose et al employ external MOSFET 165 in the reverse battery protection arrangement. Therefore, Kabushiki et al in view of Grose et al render the claim obvious.
Regarding claim 8, Kabushiki et al teach switch circuit 5 containing two N-channel MOSFETs 6a and 6b situated battery 4 and inverter circuit 1 (page 2, par. 005). Therefore, Kabushiki et al in view of Grose et al render the claim obvious.
Regarding claims 9-11, the limitations have been met above. Therefore, Kabushiki et al in view of Grose et al render the claims obvious.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Witehira et al, US Patent No. 5,175,484, disclose an electrical power distribution. Faulk, US Patent No. 5,945,806, discloses a variable-voltage programmable battery module.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL ST CYR whose telephone number is (571)272-2407. The examiner can normally be reached M to F 8:00-8:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pham Thomas can be reached at 571-272-3689. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DANIEL ST CYR
Primary Examiner
Art Unit 2876
/DANIEL ST CYR/Primary Examiner, Art Unit 2876
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