Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 30th, 2024 was filed before the mailing date of the first action on merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I and Species 1 in the reply filed on July 20th, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation, “the interconnection structures comprise rows of interconnection structures aligned parallel along the first lateral direction” is indefinite. It is unclear as to how the interconnection structures comprise rows of itself. The limitation will be interpreted as “the interconnection structures are arranged in rows along the first lateral direction”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 - 5 are rejected under 35 U.S.C. 102a(1) as being anticipated by He et al. (US 20230301053 A1; hereinafter He).
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Annotated Fig. 2D – He
Regarding claim 1, He teaches a memory device (Fig. 1-2: microelectronic device 101 that is a memory device; [0031]), comprising:
an array of memory cells in an array region (Fig. 1: array of memory cells 146; [0045]);
word lines extending parallel in a first lateral direction (Fig. 1: word lines 120 extend in a X-direction; [0037]);
bit lines extending parallel in a second lateral direction (Fig. 1: bit lines 118 extend in a Z-direction; [0037] – [0038]); and
interconnection structures located within the array region and coupled with the word lines (Fig. 2C: word line interconnect 298W connected to word lines 120 through redistribution structure pad (K0) 297 and first sub contact 295; [0064]) and
arranged in staggered columns along the second lateral direction (see annotated Fig. 2D: columns of interconnects 298 are staggered in the z-direction).
Regarding claim 2, the memory device of claim 1, wherein: a first distance between two interconnection structures coupled with two adjacent word lines is greater than a second distance between the two adjacent word lines (See annotated Fig. 2D: the distance between two interconnects is a diagonal line in the X-Y direction, the distance between two word lines 120A is the height of said diagonal line in the Y-direction, and because the distance between the two lines is only the Y-component of the diagonal line, the diagonal distance between the center of each of adjacent 298 is clearly visibly greater than the distance between adjacent word lines 120A. "[T]he description of the article pictured can be relied on, in combination with the drawings, for what they would reasonably teach one of ordinary skill in the art. In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977).", See MPEP §2125(II)).
Regarding claim 3, He teaches the memory device of claim 1, wherein: a first column of interconnection structures are located at a first side of a center position of the array region; and a second column of interconnection structures are located at a second side of the center position opposite to the first side (See annotated Fig. 2D: first side contains column of interconnect structures 298 and second side contains a separate column of interconnect structures 298).
Regarding claim 4, He teaches the memory device of claim 1, wherein: a first column of interconnection structures are located at a first side of one bit line; and a second column of interconnection structures are located at a second side of the one bit line opposite to the first side (See annotated Fig. 2D and Fig. 1: Columns of word lines are in region 106A as shown in Fig. 2D, bit lines 118A contain regions 106A in both sides in the x-direction; [0047]).
Regarding claim 5, He teaches the memory device of claim 1, further comprising: a conductive layer connected to first ends of the interconnection structures, wherein second ends of the interconnection structures are connected to the word lines (Fig. 2C: second redistribution structure 299 is connected to the word line interconnect 298W at a first end, and connected to the word line 120 by first redistribution structure pad (K0) 297 at the other end; [0064]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over He as applied to claim 1 above, and further in view of Kim et al. (US 20080239783 A1; hereinafter Kim).
Regarding claim 6, He fails to teach memory device of claim 1, wherein: the interconnection structures comprise rows of interconnection structures aligned parallel along the first lateral direction; and the interconnection structures in a same row are connected to a same word line.
However, Kim teaches wherein the interconnection structures comprise rows of interconnection structures aligned parallel along the first lateral direction; and the interconnection structures in a same row are connected to a same word line (Fig. 5 and 6A: word lines 131, 132, 133, 134, 145 and 146 are connected to multiple strapping contacts 173 and 177 in the strapping contact regions 105a-c; [0067]).
However, it would have been obvious for one of ordinary skill in the art of the claimed invention to combine the word line interconnects of He with the plurality of connections of Kim in order to provide improve the word line contact performance of the device and improve reliability in the connection to the word lines.
Regarding claim 7, He does not explicitly teach the memory device of claim 6, further comprising: a first conductive layer connected to odd numbers of rows of interconnection structures; and a second conductive layer connected to even numbers of rows of interconnection structures.
However, Kim teaches a first conductive layer connected to odd numbers of rows of interconnection structures; and a second conductive layer connected to even numbers of rows of interconnection structures (Fig. 5 and 6B: active patterns 111, 112, 113, 114, 115, 125, and 126 are connect to strapping contacts 173 and 177 in an alternating pattern where all the odd numbered active patterns 111, 113, and 125 are connected to the odd word lines, and the even active patterns 112, 114, and 126 are connected to even numbered word lines; [0065] and [0067] – [0068]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the conductive layer of He with the active patterns of Kim in order to connect multiple interconnects on the same line together and improve the line contact performance of the device.
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over He as applied to claim 1 above, and further in view of Mueller et al. (US 20150129955 A1; hereinafter Mueller).
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Annotated Fig. 2G – Mueller
Regarding claim 8, He does not explicitly teach the memory device of claim 1, wherein: each of the array of memory cells comprises a vertical transistor and a storage unit coupled with the vertical transistor; and each word line comprises gate structures of a corresponding row of vertical transistors aligned along the first lateral direction; wherein in each vertical transistor, a gate structure is located at a lateral side of a channel structure of the vertical transistor.
However, Mueller teaches wherein: each of the array of memory cells comprises a vertical transistor and a storage unit coupled with the vertical transistor (Fig. 2A: vertical memory cell 201 includes body region 206, an electrode 208, and a storage element 210, with the digit line 204, with the body region 206, and the electrode 208 forming a vertical access transistor; [0030]); and each word line comprises gate structures of a corresponding row of vertical transistors aligned along the first lateral direction (Fig. 2A and see annotated Fig. 2G: Word lines 214 function as a gate between the vertical access transistor and the storage element 210; [0030]); wherein in each vertical transistor, a gate structure is located at a lateral side of a channel structure of the vertical transistor (See annotated Fig. 2G and Fig. 2A: gate structures of word lines 214 are directly to the sides of memory cells 201 where the channel structure is in the body region 206; [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the memory device of He with the vertical transistor of Mueller in order to couple the gates of the transistors with the word lines to make the device more compact.
Regarding claim 10, He does not explicitly teach the memory device of claim 8, wherein in each vertical transistor, the gate structure laterally surrounds the channel structure of the vertical transistor.
However, Mueller teaches wherein in each vertical transistor, the gate structure laterally surrounds the channel structure of the vertical transistor (See annotated Fig. 2G and Fig. 2A: gate structure laterally surrounds the channel structure in the body region 206 of the memory cell 201 on the left and right sides; [0035]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN HOANG TRAN whose telephone number is (571)270-0290. The examiner can normally be reached 7am-5pm.
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/BENJAMIN HOANG TRAN/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
