Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on August 27, 2026, under 37 C.F.R. 1.312 has been entered. All objections raised by the examiner to the applicant’s abstract and claims in the previous office action have been addressed. Therefore, all objections to the abstract and claims are withdrawn. In addition, all rejections under 35 U.S.C. 112(b) have been addressed. Therefore, the rejections of claims 10-16 under 35 U.S.C. 112(b) have been withdrawn.
Response to Arguments
Applicant's arguments filed August 27, 2026, have been fully considered but they are not persuasive.
Regarding rejections under 35 U.S.C. 102 and 103, the applicant argues that the rejections of claims 1-8 and 10-16 under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Park et. al., Pub. No. US 2018/0366468, hereafter referred to as Park, was improper because Park fails to teach the limitation, “a first insulating film on top of each of the first, second, and third wirings”, recited in the amended claim 1, as well as the similar limitation, “a first insulating film on top of each of the first and second wirings”, recited in the amended claim 10. Because claim 9 is dependent on claim 1, the applicant further argues that the rejection of claim 9 under 35 U.S.C. 103 as being unpatentable over Park in view of Kim et. al., Pub. No. US 2021/0375896, hereafter referred to as Kim, was also improper.
In response to the arguments, the limitations recited in claims 1 and 10 in question were not recited in the original unamended claims but were only disclosed in the specification. While interpretation of the claims may be guided by the specification, claim limitations cannot be imported from the specification (see MPEP 2111.01 II: ““Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim. For example, a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment.” Superguide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875, 69 USPQ2d 1865, 1868 (Fed. Cir. 2004).”). The applicant’s argument amounts to importing limitations into the original unamended claims that were not recited in the original claims.
Furthermore, the examiner must respectfully disagree that Park fails to teach the limitations, “a first insulating film on top of each of the first, second, and third wirings”, recited in the amended claim 1, as well as the similar limitation, “a first insulating film on top of each of the first and second wirings”, recited in the amended claim 10. Under a broadest reasonable interpretation, the fourth interlayer insulating layer 369 disclosed by Park can be considered to be “on top of” the bit line BL, the peripheral conductive pattern 343bw, and the through electrode 367 by virtue of the fact that it is disposed above them; direct contact with a top surface is not required. Therefore, Park still anticipates the amended claims.
In light of the above arguments, the examiner maintains that the rejections of the original unamended claims 1-8 and 10-16 under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Park and of claim 9 under 35 U.S.C. 103 as being unpatentable over Park in view of Kim were proper. However, the applicant’s amendments to claims 1 and 10 render the original rejections moot, necessitating the new grounds of rejection detailed below.
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Fig. 17P of Park, reproduced above with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8, 10-14, and 16 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Park.
Regarding claim 1, Park teaches all of the limitations of the claim in Fig. 17P, reproduced above with annotations added by the examiner: “An apparatus” (Fig. 17P) “comprising: a semiconductor substrate” ([0085]; Fig. 17P, substrate 301) “having a first region” ([0085]; Fig. 17P, first region A1), “a second region” ([0085]; Fig. 17P, second region B1), “and a third region” ([0085]; Fig. 17P, third region C1); “a first wiring” ([0093]; Fig. 17P, bit line BL, first cell metal containing pattern 317a) “above the first region of the semiconductor substrate” (Fig. 17P; note that the bit line BL is in the first region A1 and above the substrate 301); “a second wiring” ([0097]; Fig. 17P, peripheral conductive pattern 343bw) “above the second region of the semiconductor substrate” (Fig. 17P; note that the peripheral conductive pattern 343bw is in the second region B1 and above the substrate 301); “a third wiring” ([0097]; Fig. 17P, through electrode 367) “above the third region of the semiconductor substrate” (Fig. 17P; note that the through electrode 367 is in the third region C1 and above the substrate 301); “and a first insulating film” ([0104]; Fig. 17P, fourth interlayered insulating layer 369) “on top of each of the first, second, and third wirings” (Fig. 17P; note that the fourth interlayered insulating layer 369 is above each of the bit line BL, the peripheral conductive pattern 343bw, and the through electrode 367); “wherein a height of an upper surface of the first wiring” (Fig. 17P, upper surface of the first cell metal containing pattern 317a) “is lower than a height of an upper surface of the second wiring” (Fig. 17P; note that the upper surface of the peripheral conductive pattern 343bw is higher than the upper surface of the first cell metal containing pattern 317a); “wherein the height of the upper surface of the second wiring” (Fig. 17P; upper surface of the peripheral conductive pattern 343bw) “is lower than a height of an upper surface of the third wiring” (Fig. 17P; note that the upper surface of the through electrode 367 is higher than the upper surface of the peripheral conductive pattern 343bw); “and wherein each of portions of the first insulating film disposed above the first, second, and third wirings have an equal film thickness” (Fig. 17P; note that the fourth interlayered insulating film 369 has a uniform thickness over all three of the first cell metal containing pattern 317a, the peripheral conductive pattern 343bw, and the through electrode 369).
Regarding claim 2, Park further teaches “further comprising a second insulating film” ([0104]; Fig. 17P, upper insulating layer 375) “on the first insulating film” (Fig. 17P; note that the upper insulating layer 375 is disposed on top of the fourth interlayered insulating film 369).
Regarding claim 3, Park further teaches “wherein the second wiring” ([0097]; Fig. 17P, peripheral conductive pattern 343bw) “and the third wiring” ([0097]; Fig. 17P, through electrode 367) “are included in a same layer” (Fig. 17P; note that portions of the peripheral conductive pattern 343bw and the through electrode 367 are contained within regions between the second interlayered insulating layer 329 (see [0092]) and the third interlayered insulating layer 361 (see [0102])).
Regarding claim 4, Park further teaches “wherein the first wiring” ([0093]; Fig. 17P, bit line BL, first cell metal containing pattern 317a) “is included in different layers from the second and third wirings” (Fig. 17P; note that portions of the peripheral conductive pattern 343bw and the through electrode 367 are contained within regions between the second interlayered insulating layer 329 (see [0092]) and the third interlayered insulating layer 361 (see [0102]), while the first cell metal containing pattern 317a is parallel with a portion of the second interlayered insulating layer 329).
Regarding claim 5, Park further teaches “wherein the first wiring” ([0093]; Fig. 17P, bit line BL, first cell metal containing pattern 317a) “comprises tungsten” ([0089]: “The first metal containing layer 317 may be formed of or include, for example, at least one of titanium nitride or tungsten.”; [0093]: “Thereafter, the second capping layer 331, the first capping layer 319, the first metal containing layer 317, the first polysilicon mask pattern 311, and the second polysilicon pattern 314 may be etched using the second mask pattern 333 as an etch mask, and thus, a bit line contact DC and a bit line BL, a first capping pattern 319a, and a second capping pattern 331a, which are stacked on the bit line contact DC, may be formed on the first region A1.”).
Regarding claim 6, Park further teaches “wherein the second” ([0097]; Fig. 17P, peripheral conductive pattern 343bw) “and third wirings” ([0097]; Fig. 17P, through electrode 367) “comprise tungsten” ([0096]: “The second metal containing layer 343 may be formed of or include, for example, titanium nitride or tungsten.”; [0097]: “The etching of the second metal containing layer 343 may be performed to form a peripheral conductive pattern 343bw on the second region B1 and to form a peripheral contact 343bc in the peripheral contact hole 339.”; [0103]: “A conductive layer may be formed on the semiconductor substrate 301 to fill the through electrode hole 363. The conductive layer may be formed of or include at least one of metallic materials (e.g., tungsten, aluminum, and copper). An anisotropic etching process or a polishing process may be performed on the conductive layer and the via insulating layer to expose the third interlayered insulating layer 361. Thus, the via insulating layer 365 may remain in the through electrode hole 363, and the through electrode 367 may be formed in the through electrode hole 363.”).
Regarding claim 8, Park further teaches “wherein the second insulating film” ([0104]; Fig. 17P, upper insulating layer 375) “comprises silicon nitride” ([0104]: “The upper insulating layer 375 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or polyimide.”).
Regarding claim 10, Park teaches all of the limitations of the claim in Fig. 17P: “An apparatus” (Fig. 17P) “comprising: a semiconductor substrate” ([0085]; Fig. 17P, substrate 301) “having a first region” ([0085]; Fig. 17P, first region A1) “and a second region” ([0085]; Fig. 17P, second region B1); “a first wiring” ([0093]; Fig. 17P, bit line BL, first cell metal containing pattern 317a) “above the first region of the semiconductor substrate” (Fig. 17P; note that the bit line BL is in the first region A1 and above the substrate 301); “a second wiring” ([0097]; Fig. 17P, peripheral conductive pattern 343bw) “above the second region of the semiconductor substrate” (Fig. 17P; note that the peripheral conductive pattern 343bw is in the second region B1 and above the substrate 301); “a first insulating film” ([0104]; Fig. 17P, fourth interlayered insulating layer 369) “on top of each of the first and second wirings” (Fig. 17P; note that the fourth interlayered insulating layer 369 is above each of the bit line BL and the peripheral conductive pattern 343bw); “wherein a height of an upper surface of the first wiring” (Fig. 17P, upper surface of the first cell metal containing pattern 317a) “is lower than a height of an upper surface of the second wiring” (Fig. 17P; note that the upper surface of the peripheral conductive pattern 343bw is higher than the upper surface of the first cell metal containing pattern 317a); “and wherein the first insulating film disposed above each of the first and second wirings has a same film thickness” (Fig. 17P; note that the fourth interlayered insulating film 369 has a uniform thickness over both the first cell metal containing pattern 317a and the peripheral conductive pattern 343bw).
Regarding claim 11, Park further teaches “further comprising a second insulating film” ([0104]; Fig. 17P, upper insulating layer 375) “on the first insulating film” (Fig. 17P; note that the upper insulating layer 375 is disposed on top of the fourth interlayered insulating film 369).
Regarding claim 12, Park further teaches “wherein the first wiring” ([0093]; Fig. 17P, bit line BL, first cell metal containing pattern 317a) “is included in a different layer from the second wiring” (Fig. 17P; note that portions of the peripheral conductive pattern 343bw are contained within regions between the second interlayered insulating layer 329 (see [0092]) and the third interlayered insulating layer 361 (see [0102]), while the first cell metal containing pattern 317a is parallel with a portion of the second interlayered insulating layer 329).
Regarding claim 13, Park further teaches “wherein the first wiring” ([0093]; Fig. 17P, bit line BL, first cell metal containing pattern 317a) “comprises tungsten” ([0089], [0093]).
Regarding claim 14, Park further teaches “wherein the second wiring” ([0097]; Fig. 17P, peripheral conductive pattern 343bw) “comprises tungsten” ([0096-0097]).
Regarding claim 16, Park further teaches “wherein the second insulating film” ([0104]; Fig. 17P, upper insulating layer 375) “comprises silicon nitride” ([0104]).
Claims 1, 7, 10, and 15 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Park.
Regarding claim 1, Park teaches all of the limitations of the claim in Fig. 17P: “An apparatus” (Fig. 17P) “comprising: a semiconductor substrate” ([0085]; Fig. 17P, substrate 301) “having a first region” ([0085]; Fig. 17P, first region A1), “a second region” ([0085]; Fig. 17P, second region B1), “and a third region” ([0085]; Fig. 17P, third region C1); “a first wiring” ([0093]; Fig. 17P, bit line BL, first cell metal containing pattern 317a) “above the first region of the semiconductor substrate” (Fig. 17P; note that the bit line BL is in the first region A1 and above the substrate 301); “a second wiring” ([0097]; Fig. 17P, peripheral conductive pattern 343bw) “above the second region of the semiconductor substrate” (Fig. 17P; note that the peripheral conductive pattern 343bw is in the second region B1 and above the substrate 301); “a third wiring” ([0097]; Fig. 17P, through electrode 367) “above the third region of the semiconductor substrate” (Fig. 17P; note that the through electrode 367 is in the third region C1 and above the substrate 301); “and a first insulating film” ([0104]; Fig. 17P, upper insulating layer 375) “on top of each of the first, second, and third wirings” (Fig. 17P; note that the upper insulating layer 375 is above each of the bit line BL, the peripheral conductive pattern 343bw, and the through electrode 367); “wherein a height of an upper surface of the first wiring” (Fig. 17P, upper surface of the first cell metal containing pattern 317a) “is lower than a height of an upper surface of the second wiring” (Fig. 17P; note that the upper surface of the peripheral conductive pattern 343bw is higher than the upper surface of the first cell metal containing pattern 317a); “wherein the height of the upper surface of the second wiring” (Fig. 17P; upper surface of the peripheral conductive pattern 343bw) “is lower than a height of an upper surface of the third wiring” (Fig. 17P; note that the upper surface of the through electrode 367 is higher than the upper surface of the peripheral conductive pattern 343bw); “and wherein each of portions of the first insulating film disposed above the first, second, and third wirings have an equal film thickness” (Fig. 17P; note that the upper insulating layer 375 has a uniform thickness over all three of the first cell metal containing pattern 317a, the peripheral conductive pattern 343bw, and the through electrode 369).
Regarding claim 7, Park further teaches “wherein the first insulating film” ([0104]; Fig. 17P, upper insulating layer 375) “comprises silicon dioxide” ([0104]).
Regarding claim 10, Park teaches all of the limitations of the claim in Fig. 17P: “An apparatus” (Fig. 17P) “comprising: a semiconductor substrate” ([0085]; Fig. 17P, substrate 301) “having a first region” ([0085]; Fig. 17P, first region A1) “and a second region” ([0085]; Fig. 17P, second region B1); “a first wiring” ([0093]; Fig. 17P, bit line BL, first cell metal containing pattern 317a) “above the first region of the semiconductor substrate” (Fig. 17P; note that the bit line BL is in the first region A1 and above the substrate 301); “a second wiring” ([0097]; Fig. 17P, peripheral conductive pattern 343bw) “above the second region of the semiconductor substrate” (Fig. 17P; note that the peripheral conductive pattern 343bw is in the second region B1 and above the substrate 301); “and a first insulating film” ([0104]; Fig. 17P, upper insulating layer 375) “on top of each of the first and second wirings” (Fig. 17P; note that the upper insulating layer 375 is above each of the bit line BL and the peripheral conductive pattern 343bw); “wherein a height of an upper surface of the first wiring” (Fig. 17P, upper surface of the first cell metal containing pattern 317a) “is lower than a height of an upper surface of the second wiring” (Fig. 17P; note that the upper surface of the peripheral conductive pattern 343bw is higher than the upper surface of the first cell metal containing pattern 317a); “and wherein the first insulating film disposed above each of the first and second wirings has a same film thickness” (Fig. 17P; note that the upper insulating layer 375 has a uniform thickness over both the first cell metal containing pattern 317a and the peripheral conductive pattern 343bw).
Regarding claim 15, Park further teaches “wherein the first insulating film” ([0104]; Fig. 17P, upper insulating layer 375) “comprises silicon dioxide” ([0104]).
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Figure 1: Fig. 2 of Kim, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim.
Regarding claim 9, Park teaches “The apparatus of claim 1, wherein the first wiring” (Park [0093]; Fig. 17P, bit line BL, first cell metal containing pattern 317a) “is a part of a memory cell array structure” (Park [0038]: “Hereinafter, a dynamic random access memory (DRAM) device will be described as an example of the semiconductor device.”, [0085]: “The first region A1 may be, for example, a cell array region.”; Fig. 17P, first region A1), “and the third wiring” ([0097]; Fig. 17P, through electrode 367) “is part of a peripheral circuit structure” (Park [0085]: “The third region C1 may be, for example, a region, on which a through electrode will be formed.”; Fig. 17P, third region C1; note that such a region can still be interpreted as a “peripheral circuit structure”), but does not teach “the second wiring is a part of either one of a sense amplifier or a sub-word driver coupled to the memory cell structure”.
Kim, on the other hand, teaches a device consisting of a memory cell (Kim [0019]; Fig. 2, reproduced above with annotations added by the examiner, cell array region CAR) and a peripheral circuit region (Kim [0019]; Fig. 2, peripheral circuit region PCR). Furthermore, Kim teaches that the peripheral circuit region may include a sense amplifier (Kim [0019]: “The peripheral circuit region PCR may include a word line driver, a sense amplifier, row and column decoders, and control circuits.”).
The sense amplifier of Kim may be incorporated into the device of Park by making the second region B1 of Park a sense amplifier. The combined device teaches “the second wiring” (Park [0097]; Fig. 17P, peripheral conductive pattern 343bw) “is a part of either one of a sense amplifier or a sub-word driver coupled to the memory cell structure” (Kim [0019]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use a sense amplifier circuit as taught by Kim as the second region B1 of the device of Park because such a circuit would serve to amplify small electrical signals from the memory cell structure to be interpreted by logic circuits and it would be a simple combination of elements of the two disclosures.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571)272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./ Examiner, Art Unit 2818
/STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818
