DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-11, Species D with newly added claims 21-23 in the reply filed on 06/24/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the mask including an opening at region 302 as described in the specification [0055]. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al US 2020/0251565.
Regarding claim 8, Su et al. in Figs. 3A-3I and [0047]-[0059] disclose a method, comprising:
forming a trench 202a, 202b in a semiconductor substrate 200/202 [0049];
lining sidewalls and a bottom of the trench 202a, 202b with a first insulating layer 208 [0051];
filling the trench 202a, 202b with a first polysilicon material 304 [0052];
selectively recessing the first polysilicon material 304 in the trench 202b at a first region of the semiconductor substrate 200/202 to a first level [0052];
selectively recessing the first polysilicon material 304 in the trench at a second region 202a of the semiconductor substrate to a second level, said second level being greater in depth than said first level Fig. 3E, [0052];
selectively recessing an upper portion of the first insulating layer 208 in said trench 202a, 202b to a first depth in the first region 202b and to a second depth in the second region 202a in order to expose an upper portion of the recessed first polysilicon material 304 in an upper portion of said trench 202a, 202b Fig. 3F, [0053];
converting the exposed upper portion of the first polysilicon material in said trench to a polyoxide material 212 (e.g. oxidized polysilicon) Fig. 3G, [0054] ;
lining sidewalls and a bottom of the upper portion of said trench with a second insulating layer 210 Fig. 3G, [0054]; and
filling the upper portion of said trench 202a, 202b with a second polysilicon material 206.
Regarding claim 9, Su et al. in Figs. 3A-3I and [0047]-[0059] disclose the method of claim 8, wherein a remaining portion of the first polysilicon material in said trench forms a transistor field plate electrode 204, and wherein the second polysilicon material forms a transistor gate electrode 206.
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Regarding claim 10, Su et al. in Figs. 3A-3I and [0047]-[0059] disclose the method of claim 9, wherein the second polysilicon material that forms the transistor gate electrode 206 includes a first gate lobe on one side of the polyoxide material 212, a second gate lobe on an opposite side of the polyoxide material, and a gate bridge extending over the polyoxide material Fig. 3I, annotated above, [0056]-[0057].
Allowable Subject Matter
Claims 1-7 and 21-23 are allowed over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: The prior art neither anticipates nor renders obvious, in the context of the claims,
Regarding claim 1, forming a mask covering the trench at a first region of the semiconductor substrate, said mask including a first opening over the trench at a second region of the semiconductor substrate; using said first opening, etching to selectively remove a first portion of the first polysilicon material at said second region of the semiconductor substrate; removing the mask; etching to selectively remove a second portion of the first polysilicon material at said first region of the semiconductor substrate and selectively remove a third portion of the first polysilicon material at said second region of the semiconductor substrate.
Regarding claim 21, forming a mask covering the second trench, said mask including an opening over the first trench; using said opening, applying a first etch to selectively remove a first portion of the first polysilicon material from the first trench; removing the mask; applying a second etch at the first trench and second trench to selectively remove: a second portion of the first polysilicon material from the first trench and a third portion of the first polysilicon material from the second trench; applying a third etch at the first trench and second trench to selectively remove: an upper portion of the first insulating layer in the first trench to a first depth and an upper portion of the first insulating layer in the second trench to a second depth.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art neither anticipates nor renders obvious, in the context of the claims,
forming a stack of insulating layers covering the transistor gate electrode, the trench and the semiconductor substrate; at said second region, forming an opening aligned with the trench and extending through the stack of insulating layer and partially extending into the gate bridge; and forming a gate contact in said opening.
Although various prior art references disclose several individual limitations in the claims, these references, and their combinations, neither anticipate nor render obvious the above identified limitation(s), as structured and interrelated in the context of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898
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