DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/21/26 has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-7, 15-17, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ban (US 20090198858) in view of Lee (US 20160232112).
With respect to claim 1, the Ban reference teaches an apparatus, comprising:
a memory device; (e.g. fig. 1a, memory device 1) and
a buffer; (e.g. fig. 2, I/O buffer 22; and paragraph 110)
a controller (e.g. fig. 1a, memory controller 100) coupled to the memory device configured to:
perform operations on the memory device and the volatile memory of the buffer according to a burst length signal that indicates a burst length. (paragraph 28, where the interface section includes an interpretation block configured to carry out interpretation of a mode representative of one of the memory types from a mode designation signal, carry out identification at least of a burst length and a bit width of the data and output a result of the identification as access information for the memory array to the converter, and the converter issues a command and an address for the memory array based on the mode interpretation and the information of the burst length and the bit width from the interpretation block and outputs the access data after varying the data width of the access data or without varying the data width)
However, the Ban reference does not explicitly teach that the memory device including an array of non-volatile memory cells; the buffer including volatile memory, wherein the buffer is used to buffer data during execution of read commands and write commands; and wherein the burst length signal is based on a type of the memory on which a command associated with the burst length signal will be executed. (emphasis added)
The Lee reference teaches it is conventional to have the memory device including an array of non-volatile memory cells; (e.g. fig. 4a, NAND 470) the buffer including volatile memory (e.g. fig. 4a, DRAM 450/460), wherein the buffer is used to buffer data during execution of read commands and write commands; (paragraph 76, where the DRAM buffers are host memories to support 2 hop DMA/rDMA read/write data traffics between the IOC(s) (40 GbE or FC-16×4) and the NVM/SSD storage devices. The PCIe controller may directly DMA read/write to the DRAM buffers for relaying the data from/to the IOCs to the SSD.NVM devices) and wherein the burst length signal is based on a type of the memory on which a command associated with the burst length signal will be executed. (paragraph 49, where the DDR4-SSDs or NVMs (e.g., NAND or NVM chips) may have the same bus speed but with block read/write accesses such that one CMD/address may handle a longer burst of data and use the DRAM/NVM random access waiting time slot (e.g., BL32 for 256 B, burst read/write inserted in between BL8 read/write intervals; and paragraph 48, where the burst length of the DRAM devices or NVM devices may be different from BL8 and the burst lengths of the SSDs may be different from BL32 [which shows different burst lengths for different types of memories])
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Ban reference to have the memory device including an array of non-volatile memory cells; the buffer including volatile memory, wherein the buffer is used to buffer data during execution of read commands and write commands; and wherein the burst length signal is based on a type of the memory on which a command associated with the burst length signal will be executed, as taught by the Lee reference.
The suggestion/motivation for doing so would have been to allow inserting SSD/NVM block burst read/write operations between RAM/NVM random read-write operation waiting time slots, which allows UMI bus operations to efficiently interleave different types of memory operation cycles. (Lee, paragraph 32)
Therefore it would have been obvious to combine the Ban and Lee references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the Ban and Lee references teaches the apparatus of claim 1, wherein the controller receives commands from a host with the burst length signal. (Ban, paragraph 109, where adaptive converter 31 has a function of carrying out a process of issuing a command and an address based on information of the burst length and the bit width of input data identified by the mode interpretation block 25 and outputting the data after varying the data or without varying the data)
With respect to claim 3, the Ban and Lee references teaches the apparatus of claim 1, wherein the burst length signal is based on a type of operation performed by the memory device. (Ban, paragraph 109, where adaptive converter 31 has a function of carrying out a process of issuing a command and an address based on information of the burst length and the bit width of input data identified by the mode interpretation block 25 and outputting the data after varying the data or without varying the data)
With respect to claim 5, the Ban and Lee references teaches the apparatus of claim 1, wherein the burst length signal is based on a size of request in a command. (Ban, paragraph 29, where the converter carries out the variation process of the data width when the external data bus width and the data bus width of the memory array are different from each other)
With respect to claim 6, the Ban and Lee references teaches the apparatus of claim 1, wherein the burst length signal is based on a desired bandwidth for the memory device when performing the operations. (Ban, fig. 27a/b and 28a; and paragraph 281, where timings of reading/writing processes of the SDR and the DDR are described with reference to FIGS. 27A, 27B and 28A)
With respect to claim 7, the Ban and Lee references teaches the apparatus of claim 1, wherein the burst length signal is based on a desired latency for the memory device when performing the operations. (Ban, paragraph 282, where FIGS. 27A and 27B illustrate an example of a read cycle timing and a write cycle timing of an ordinary SDR-SDRAM. Particularly, FIGS. 27A and 27B illustrate an example of timings of the system clock CLK, command CMD and input/output data DQ where the CAS latency CL=2 and the burst length BL is 4)
Claims 15-17 and 19 are the method implementation of claims 1-7, and rejected under a similar rationale as shown in the rejections above.
With respect to claim 20, the combination of the Ban and Lee references further teaches the method of claim 15, further including receiving another burst length signal to change the burst length for the memory device. (Ban, paragraph 143, where the mode interpretation block 25 identifies the burst length and the bit width of input data included in an input mode designation signal and supplies the identified information as the mode signal Smd to the adaptive converter 31)
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 6-7 of the remarks) and amendments with respect to claim 1 have been considered but are not persuasive. Applicant argues “Ban's controller does not -- and cannot -- "perform operations on ... the volatile memory of the buffer" as recited by claim 1, because Ban's IO buffer 22 has no volatile memory upon which to perform operations.” The Examiner respectfully disagrees. The Examiner notes the Lee reference was included to teach the buffer includes a volatile memory; and wherein the buffer is used to buffer data during execution of read commands and write commands. (see fig. 4a, DRAM 450/460; and paragraph 76, where the DRAM buffers are host memories to support 2 hop DMA/rDMA read/write data traffics between the IOC(s) (40 GbE or FC-16×4) and the NVM/SSD storage devices. The PCIe controller may directly DMA read/write to the DRAM buffers for relaying the data from/to the IOCs to the SSD.NVM devices) Thus, in view of the citations above from the Lee reference, it is clear that the buffer can be a volatile memory and be used to buffer data during execution of read commands and write commands. Also, it appears that the applicant's arguments are against the references individually, and one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant also argues (see page 7 of the remarks) “Ban or Lee or any combination thereof, of a burst length that is "based on a type of memory on which a command associated with the burst length signal will be executed" in the context of performing operations on both the non-volatile memory cells of a memory device and the volatile memory of a buffer”. The Examiner respectfully disagrees. The Lee reference teaches (paragraph 49) that the DDR4-SSDs or NVMs (e.g., NAND or NVM chips) may have the same bus speed but with block read/write accesses such that one CMD/address may handle a longer burst of data and use the DRAM/NVM random access waiting time slot (e.g., BL32 for 256 B, burst read/write inserted in between BL8 read/write intervals; and paragraph 48, where the burst length of the DRAM devices or NVM devices may be different from BL8 and the burst lengths of the SSDs may be different from BL32. Thus, in view of the citations above, the Lee reference shows that there are different burst lengths for different types of memories, which teaches the limitation argued above.
Lastly, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the Applicant argues “no proper motivation to combine Ban and Lee in the manner asserted”. The Examiner respectfully disagrees. The Lee reference teaches (paragraph 32) a motivation of allow inserting SSD/NVM block burst read/write operations between RAM/NVM random read-write operation waiting time slots, which allows UMI bus operations to efficiently interleave different types of memory operation cycles.
Any other arguments pertaining to claim 15 and the dependent (see page 8) have been considered, and the Examiner notes the responses above.
3. CLOSING COMMENTS
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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