Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 06 June 2025. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4, 7 – 10, 12 – 15, 17 – 19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US20200074019A1 (Amaru) in view of US20240020096A1 (Chen).
In regards to claim 1 (Amaru) shows:
A method performed by one or more computers, the method comprising; Amaru [0103] and [0104] teach a computer system with a processor that loads an IC design tool into memory and runs it to perform logic optimization of an IC design.
obtaining a description of an integrated circuit (IC); Amaru [0034] and [0035] teach writing hardware description language code that describes the functionality of the IC design and translating that code into a netlist during synthesis.
selecting one or more Boolean expressions specified in the description; Amaru [0072] and [0083] teach selecting nodes of the logic network, each node defined by a Boolean formula for logic functions f and g, as candidates for Boolean resubstitution.
Amaru differs from the claimed invention in that it does not explicitly disclose processing the one or more selected Boolean expressions using a neural network to generate an output that comprises one or more alternative Boolean expressions.
Chen teaches processing the one or more selected Boolean expressions using a neural network to generate an output that comprises one or more alternative Boolean expressions; Chen [0047], [0071], [0078], and [0086] teach a trained transformer-based model that receives a user-selected portion of existing code and generates alternative code that performs the same function with less redundancy and complexity.
It would have been obvious to one of ordinary skill in the art to combine Amaru and Chen to generate the alternative Boolean expressions of the selected logic with a trained neural network, with a reasonable expectation of success as both references address automated rewriting of code into a more efficient form that keeps the same function.
In regards to claim 2 (Amaru) shows the method of claim 1:
wherein the description of the integrated circuit comprises a Register Transfer Level (RTL) description or a gate-level netlist description; Amaru [0035] and [0039] teach translating the HDL code into a gate-level netlist of AND gates, OR gates, and other logic blocks, and checking the netlist against the RTL design.
In regards to claim 3 (Amaru) does not show: wherein obtaining the description of the IC comprises receiving the description from a client device;
Chen teaches wherein obtaining the description of the IC comprises receiving the description from a client device; Chen [0086] and [0149] teach receiving code that a user selects or enters on the user's computer, with processing performed partly on that computer and partly on a remote server.
It would have been obvious to one of ordinary skill in the art to combine Amaru and Chen to receive the IC description from a user's client device, with a reasonable expectation of success as both references address software tools that process code supplied by a user.
In regards to claim 4 (Amaru) shows the method of claim 1:
wherein each alternative Boolean expression is a simplified representation that has fewer Boolean operators than a corresponding Boolean expression but represents a same logical function as the corresponding Boolean expression; Amaru [0070], [0072], [0073], and [0080] teach re-expressing function f as the XOR of its Boolean difference with g, which keeps the same logic function while reducing the total number of nodes, each node being a 2-input AND or OR gate, and accepting the new implementation only if the size decreases.
In regards to claim 7 (Amaru) shows the method of claim 1:
further comprising modifying the description of the integrated circuit by replacing the one or more Boolean expression with the alternative Boolean expressions; Amaru [0083] and [0085] teach replacing the selected sub-networks in the logic network with the optimized sub-network when doing so reduces the size of the logic network.
In regards to claim 8 (Amaru) shows the method of claim 7:
further comprising providing the modified description for use in fabricating the IC; Amaru [0038], [0039], and [0104] teach passing the optimized netlist on to placement, routing, and tape-out to produce the masks used to fabricate the IC chips.
In regards to claim 9 (Amaru) shows the method of claim 8:
further comprising fabricating the IC based on the modified description; Amaru [0030] and [0104] teach fabricating IC chips from the finalized IC design, with the resulting chips improved by the logic optimization.
In regards to claim 10 (Amaru) does not show: wherein the neural network is an auto-regressive language model neural network;
Chen teaches wherein the neural network is an auto-regressive language model neural network; Chen [0104], [0105], and [0139] teach a trained model built from transformer decoder layers with masked self-attention that generates its output sequentially, such as a GPT model or other autoregressive model.
It would have been obvious to one of ordinary skill in the art to combine Amaru and Chen to use an autoregressive language model as the neural network, with a reasonable expectation of success as both references address automated rewriting of code into a more efficient form.
In regards to claim 12 (Amaru) shows:
A system comprising one or more computers and one or more storage devices storing instructions that when executed by the one or more computers cause the one more computers to perform operations comprising; Amaru [0103] and [0104] teach a computer system having a processor, memory, and a storage device that stores an IC design tool, which the processor loads and runs to perform the logic optimization operations.
obtaining a description of an integrated circuit (IC); Amaru [0034] and [0035] teach writing hardware description language code that describes the functionality of the IC design and translating that code into a netlist during synthesis.
selecting one or more Boolean expressions specified in the description; Amaru [0072] and [0083] teach selecting nodes of the logic network, each node defined by a Boolean formula for logic functions f and g, as candidates for Boolean resubstitution.
Amaru differs from the claimed invention in that it does not explicitly disclose processing the one or more selected Boolean expressions using a neural network to generate an output that comprises one or more alternative Boolean expressions.
Chen teaches processing the one or more selected Boolean expressions using a neural network to generate an output that comprises one or more alternative Boolean expressions; Chen [0047], [0071], [0078], and [0086] teach a trained transformer-based model that receives a user-selected portion of existing code and generates alternative code that performs the same function with less redundancy and complexity.
It would have been obvious to one of ordinary skill in the art to combine Amaru and Chen to generate the alternative Boolean expressions of the selected logic with a trained neural network, with a reasonable expectation of success as both references address automated rewriting of code into a more efficient form that keeps the same function.
In regards to claim 13 (Amaru) shows the system of claim 12:
wherein the description of the integrated circuit comprises a Register Transfer Level (RTL) description or a gate-level netlist description; Amaru [0035] and [0039] teach translating the HDL code into a gate-level netlist of AND gates, OR gates, and other logic blocks, and checking the netlist against the RTL design.
In regards to claim 14 (Amaru) does not show: wherein obtaining the description of the IC comprises receiving the description from a client device;
Chen teaches wherein obtaining the description of the IC comprises receiving the description from a client device; Chen [0086] and [0149] teach receiving code that a user selects or enters on the user's computer, with processing performed partly on that computer and partly on a remote server.
It would have been obvious to one of ordinary skill in the art to combine Amaru and Chen to receive the IC description from a user's client device, with a reasonable expectation of success as both references address software tools that process code supplied by a user.
In regards to claim 15 (Amaru) shows the system of claim 12:
wherein each alternative Boolean expression is a simplified representation that has fewer Boolean operators than a corresponding Boolean expression but represents a same logical function as the corresponding Boolean expression; Amaru [0070], [0072], [0073], and [0080] teach re-expressing function f as the XOR of its Boolean difference with g, which keeps the same logic function while reducing the total number of nodes, each node being a 2-input AND or OR gate, and accepting the new implementation only if the size decreases.
In regards to claim 17 (Amaru) shows the system of claim 12:
wherein the operations further comprise modifying the description of the integrated circuit by replacing the one or more Boolean expression with the alternative Boolean expressions; Amaru [0083] and [0085] teach replacing the selected sub-networks in the logic network with the optimized sub-network when doing so reduces the size of the logic network.
In regards to claim 18 (Amaru) shows the system of claim 17:
wherein the operations further comprise providing the modified description for use in fabricating the IC; Amaru [0038], [0039], and [0104] teach passing the optimized netlist on to placement, routing, and tape-out to produce the masks used to fabricate the IC chips.
In regards to claim 19 (Amaru) shows the system of claim 17:
wherein the operations further comprise fabricating the IC based on the modified description; Amaru [0030] and [0104] teach fabricating IC chips from the finalized IC design, with the resulting chips improved by the logic optimization.
In regards to claim 21 (Amaru) shows:
One or more computer storage media storing instructions that when executed by one or more computers cause the one more computers to perform operations comprising; Amaru [0103] and [0104] teach a storage device that stores an IC design tool which, when loaded and run by the processor of the computer system, performs the logic optimization operations.
obtaining a description of an integrated circuit (IC); Amaru [0034] and [0035] teach writing hardware description language code that describes the functionality of the IC design and translating that code into a netlist during synthesis.
selecting one or more Boolean expressions specified in the description; Amaru [0072] and [0083] teach selecting nodes of the logic network, each node defined by a Boolean formula for logic functions f and g, as candidates for Boolean resubstitution.
Amaru differs from the claimed invention in that it does not explicitly disclose processing the one or more selected Boolean expressions using a neural network to generate an output that comprises one or more alternative Boolean expressions.
Chen teaches processing the one or more selected Boolean expressions using a neural network to generate an output that comprises one or more alternative Boolean expressions; Chen [0047], [0071], [0078], and [0086] teach a trained transformer-based model that receives a user-selected portion of existing code and generates alternative code that performs the same function with less redundancy and complexity.
It would have been obvious to one of ordinary skill in the art to combine Amaru and Chen to generate the alternative Boolean expressions of the selected logic with a trained neural network, with a reasonable expectation of success as both references address automated rewriting of code into a more efficient form that keeps the same function.
Claims 5, 6, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over US20200074019A1 (Amaru) in view of US20240020096A1 (Chen) and further in view of US20180096619A1 (Fuka).
In regards to claim 5 (Amaru modified by Chen) does not show: wherein the output further comprises, for each alternative Boolean expression, one or more Boolean algebra rules to apply to the corresponding Boolean expression to generate the alternative Boolean expression;
Fuka teaches wherein the output further comprises, for each alternative Boolean expression, one or more Boolean algebra rules to apply to the corresponding Boolean expression to generate the alternative Boolean expression; Fuka [0141] and [0143] teach generating a solution for a logic expression built from AND, OR, and NOT operators in which each output step names the logic rule, such as simplification, conjunctive addition, or double negation, that is applied to the expression to produce the resulting expression.
It would have been obvious to one of ordinary skill in the art to further combine Amaru and Chen with Fuka to output the logic rules applied to reach each alternative Boolean expression so that each step can be checked, with a reasonable expectation of success as the references address automated transformation of logic and code expressions.
In regards to claim 6 (Amaru modified by Chen) does not show: wherein the one or more Boolean algebra rules included in the output are arranged in a determined order of application of the Boolean algebra rules;
Fuka teaches wherein the one or more Boolean algebra rules included in the output are arranged in a determined order of application of the Boolean algebra rules; Fuka [0140] and [0143] teach working out the ordered steps of a multi-step solution, applying the simplification rule in step 1 and the conjunctive addition rule in step 2.
It would have been obvious to one of ordinary skill in the art to further combine Amaru and Chen with Fuka to list the applied logic rules in their order of application so the derivation can be followed step by step, with a reasonable expectation of success as the references address automated transformation of logic and code expressions.
In regards to claim 16 (Amaru modified by Chen) does not show: wherein the output further comprises, for each alternative Boolean expression, one or more Boolean algebra rules to apply to the corresponding Boolean expression to generate the alternative Boolean expression;
Fuka teaches wherein the output further comprises, for each alternative Boolean expression, one or more Boolean algebra rules to apply to the corresponding Boolean expression to generate the alternative Boolean expression; Fuka [0141] and [0143] teach generating a solution for a logic expression built from AND, OR, and NOT operators in which each output step names the logic rule, such as simplification, conjunctive addition, or double negation, that is applied to the expression to produce the resulting expression.
It would have been obvious to one of ordinary skill in the art to further combine Amaru and Chen with Fuka to output the logic rules applied to reach each alternative Boolean expression so that each step can be checked, with a reasonable expectation of success as the references address automated transformation of logic and code expressions.
Claims 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20200074019A1 (Amaru) in view of US20240020096A1 (Chen) and further in view of US20230244938A1 (Wei).
In regards to claim 11 (Amaru modified by Chen) does not show: wherein the auto-regressive language model neural network is pre-trained on text data and then fine-tuned or few-shot learned using a plurality of Boolean expression training tuples, and wherein each Boolean expression training tuple comprises (i) a Boolean expression (ii) a simplified Boolean expression and (iii) a set of one or more Boolean algebra rules to apply to the Boolean expression to generate the simplified Boolean expression;
Wei teaches wherein the auto-regressive language model neural network is pre-trained on text data and then fine-tuned or few-shot learned using a plurality of Boolean expression training tuples, and wherein each Boolean expression training tuple comprises (i) a Boolean expression (ii) a simplified Boolean expression and (iii) a set of one or more Boolean algebra rules to apply to the Boolean expression to generate the simplified Boolean expression; Wei [0039], [0056], [0059], and [0109] teach a language model pretrained on web pages, books, and other text that is few-shot prompted with instructive sequences, each made of an instructive query, an instructive trace of the intermediate steps, and an instructive response, including for logic and mathematical queries.
It would have been obvious to one of ordinary skill in the art to further combine Amaru and Chen with Wei to adapt the pretrained language model with examples that pair an input expression with its transformation steps and result, with a reasonable expectation of success as the references address automated transformation of logic and code expressions into improved forms.
In regards to claim 20 (Amaru modified by Chen) does not show: wherein the neural network is an auto-regressive language model neural network that has been pre-trained on text data and then fine-tuned or few-shot learned using a plurality of Boolean expression training tuples, and wherein each Boolean expression training tuple comprises (i) a Boolean expression (ii) a simplified Boolean expression and (iii) a set of one or more Boolean algebra rules to apply to the Boolean expression to generate the simplified Boolean expression;
Wei teaches wherein the neural network is an auto-regressive language model neural network that has been pre-trained on text data and then fine-tuned or few-shot learned using a plurality of Boolean expression training tuples, and wherein each Boolean expression training tuple comprises (i) a Boolean expression (ii) a simplified Boolean expression and (iii) a set of one or more Boolean algebra rules to apply to the Boolean expression to generate the simplified Boolean expression; Wei [0039], [0056], [0059], [0093], and [0109] teach a left-to-right, decoder-only transformer language model pretrained on web pages, books, and other text that is few-shot prompted with instructive sequences, each made of an instructive query, an instructive trace of the intermediate steps, and an instructive response, including for logic and mathematical queries.
It would have been obvious to one of ordinary skill in the art to further combine Amaru and Chen with Wei to adapt the pretrained language model with examples that pair an input expression with its transformation steps and result, with a reasonable expectation of success as the references address automated transformation of logic and code expressions into improved forms.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/
Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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