DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "the mask" in Line 5. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the mask in Claim 16 will be interpreted as “a mask” that is different from “a single mask” mentioned in Claim 15.
Claim 19 recites the limitation that “the forming of coplanar upper surfaces of the spacer and dielectric layer also forms the first electrode”. The specifications describe the first electrode 110 (shown in the claimed invention Figs 1 and 2) as being formed using a “processing method of forming the MIM capacitor [using] a single mask” [0036], and subsequently describe that ‘the first electrode may be formed by a blanket etching process” [0037]. The blanket etching process would require no mask, so these methods of formation of the first electrode appear to be distinct. Thus, it is unclear, even in light of the specifications, how the method of Claim 19 “forms the first electrode of the MIM capacitor” that was already claimed to be formed “using a single mask” in Claim 13, from which Claim 19 depends. It is the opinion of the examiner, in light of the specifications, drawings, and analogous language of other claims, that the “forming of coplanar upper surfaces” in Claim 19 also forms, perhaps, the outer perimeter of “the first electrode of the MIM capacitor”, not the electrode itself, which has already been formed by Claims 13-15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 13-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhang US 2019/0013269 A1, hereafter referred to as "Zhang".
In regard to Claim 1, Zhang discloses a structure (Fig 4, 5, and 7) comprising: a metal-insulator-metal (MIM) capacitor (elements 22, 24, 26), including a first electrode 22 and a second electrode 26 over the first electrode, a conductive via (Fig 5 element 52) laterally adjacent to the second electrode 26 and electrically connected to the first electrode (the conductive via 52 is in contact with the first electrode 22); and a void (Fig 4 element 50, also shown in Fig 5 without numeric label) extends around an outer perimeter of the second electrode 26. The conductive via, Fig 5 element 52 in Zhang, is described as a “sacrificial layer” that “may be comprised of, for example, an organic planarization layer (OPL)” [Col 4 line 36] which may have low intrinsic conductivity, but in the broadest reasonable interpretation covers the limitation in Claim 1.
In regard to Claim 2, Zhang discloses the structure of claim 1, wherein the first electrode comprises an outer perimeter, and the other perimeter of the second electrode (26) is within the outer perimeter of the first electrode (22).
In regards to Claim 13, Zhang [Col 3 lines 35-40, Col 4 lines 31-45] discloses a method, comprising: forming a metal-insulator-metal (MIM) capacitor (Fig 5) including a first electrode (22) and a second electrode (26) over the first electrode; forming a conductive via (52) laterally adjacent to the first electrode and electrically connected to the first electrode, and forming a void (Fig 4 element 50) extending around an outer perimeter of the second electrode (26).
Regarding Claim 14, Zhang discloses the method of Claim 13, wherein the first electrode (22) comprises an upper surface area and the second electrode (26) comprises a bottom surface area that is smaller than the upper surface of the first electrode (shown in Fig 5).
Regarding Claim 15, Zhang teaches the method of Claim 13, wherein forming the MIM capacitor (Fig 2 element 32) comprises using a single mask ((Fig 2A) and [Col 3 lines 35-40]).
In regards to Claim 16, Zhang teaches the method of Claim 15 further comprising: depositing a first conductor layer (22), depositing a second conductor layer (26) over the first conductor layer, depositing a dielectric layer (28) on the second conductor layer; using a mask to form an opening at least through the dielectric layer (28) and the second conductor layer (26) (In the instant application [0021], Fig 2 mask 118 is used to protect layer 116 using etching, Zhang Fig 5, sacrificial layer 52 is used to protect layer 36 during etching, while the opening 54 is formed through the dielectric layer 28 and the second conductor layer 26. Thus, in this case, the sacrificial layer functions as a mask and serve the same purpose as mask layer 118 of the instant application.), and recessing the second conductor layer relative to the first conductor layer to define a void that is offset laterally from the opening to form the second electrode ([Col 4 lines 23-25] “an etching process is used to recess the layer 26 laterally to form a cavity 50 in the layer stack of the MIM capacitor” shown in Fig 4 element 50).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang further in view of Cheng US 9,536,982 B1, hereinafter referred to as “Cheng”.
Regarding Claim 3, Zhang discloses the structure of Claim 2; however, Zhang fails to disclose the void being laterally between the conductive via and the second electrode.
Cheng, in the same field of endeavor, discloses a structure, Cheng Fig 10B, wherein a void (“airgap” element 35 described [Col 4 lines 58-65 and Col 13 lines 42-45]) is laterally between a conductive via 55a and a second electrode (source 15a, drain 15b, and functional gate 25 elements are all electrodes located laterally around the airgap 35). Cheng discloses the function of the airgap, or void, elements “are suitable for reducing device capacitance in semiconductor devices” [Col 4 lines 58-60]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, to combine the structure of Zhang with Cheng’s airgap, or void, to disclose the structure of claim 2, wherein the void is laterally between the conductive via and the second electrode, to reduce device capacitance [Col 4 lines 58-60].
Regarding Claim 4, Zhang, as modified by Cheng, discloses the structure of Claim 3, wherein the void is within the outer perimeter of the first electrode. With the aforementioned structure of Zhang in Claims 1 and 2, then modifying Zhang to include the void disclosed by Cheng in the location specified in Claim 3, the limitations of Claim 4 are met.
Regarding Claim 5, Zhang discloses, in Fig 7, the structure of claim 1, wherein the MIM capacitor 32 further comprises a capacitor insulator 24 between the first electrode and the second electrode, further comprising a dielectric layer 28 on the second electrode. The structure of Zhang, modified by Cheng, further discloses the structure in the previous 3 lines wherein the void is surrounded by the dielectric layer 28 from above and the capacitor insulator 24 from below.
Regarding Claims 6, Zhang, as modified by Cheng, discloses in Zhang Fig 7 with the airgap disclosed in Cheng Fig 10B, the structure of claim 5 further comprising: a first spacer component (Zhang Fig 7 element 60), and the first spacer component is laterally between the conductive via and the void.
Regarding Claim 7, Zhang, as modified by Cheng, discloses the structure of Claim 6, as described in Zhang [Col 4 lines 64-65 to Col 5 line 3-4 and Fig 7] that the spacer elements 60 on either side of the conductive via 62 “extend about the circumference of the via opening”, thus further comprising a second spacer component 60 laterally surrounding the first spacer component 60 and the first electrode 22.
Regarding Claim 8, Zhang, as modified by Cheng, discloses structure of Claim 7, wherein the second spacer component (Fig 7 element 60) includes an outer side surface coplanar with a side surface of the first electrode 22. These elements share a plane along their outer surfaces where the conductive via 62 meets them in Fig 7.
Regarding Claim 17, Zhang, by itself discloses the method of forming a MIM capacitor given in Claims 13 through 16, then Zhang, as modified by Cheng, discloses the method of claim 16, further comprising depositing a spacer material over the first conductor layer (Zhang Fig 7 element 60) and filling the opening (Zhang Fig 5-Fig 7) to seal the void (which would be formed between the spacer 60 and second electrode 26 in Zhang Fig 7) laterally between the spacer material and the second electrode. Cheng [Col 1 lines 37-41 and Col 10 lines 25-35] discloses a method for depositing a conformal dielectric material 30 to enclose the air gap 35 as shown in Figure 10B.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Cheng, and further in view of Divakaruni US 2010/0163949 A1, hereafter referred to as “Diva”.
Regarding Claim 10-12, Zhang as modified by Cheng, discloses the structure of claim 8; however, the combined references fail to explicitly disclose the conductive via (62 in Fig 7 of Zhang) including a first protrusion that extends towards the second electrode.
However, in the same field of endeavor, Diva discloses in Diva Fig 7A-8A a conductive via 28” (center conductive via) including two protrusions that extend laterally outward from the conductive via [Diva 0047 and 0051]. These protrusions exist because of the shape the conductive via takes as it is formed; this may also be the case in the instant application, which would result in more efficient and cost-effective manufacturing of such semiconductor structures. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to allow the conductive via to have a variety of different shapes and contours, such as one including two protrusions outward, to optimize the manufacturing process [Diva 0048].
Therefore, regarding Claim 10, Zhang Fig 7 as modified by Cheng discloses structure of Claim 8, further modified by Diva wherein the the conductive via 62 includes a first protrusion, and the first protrusion extends towards the second electrode 26.
Regarding Claim 11, Zhang, as modified by Cheng and Diva, discloses the structure of Claim 10, wherein the first protrusion (from the conductive via 62) laterally contacts the first spacer component 60 in Zhang Fig 7.
Regarding Claim 12, Zhang, as modified by Cheng and Diva, discloses the structure of Claim 11, wherein the conductive via further comprises a second protrusion at an opposite side of the first protrusion and the second protrusion laterally contacts the second spacer component. The second protrusion would extend from Zhang’s conductive via, element 62 in Fig 7, and laterally contact the second spacer component 60 opposite the first spacer component 60 located across the conductive via.
Allowable Subject Matter
Claims 9, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claims 9 and 18, Zhang as modified by Cheng fails to disclose the first and second spacer elements having upper surfaces coplanar with the upper surface of the dielectric layer. This structure is not anticipated or made obvious in the prior art.
Claim 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding Claim 20, the rejection of Claim 19 under 35 U.S.C. 112(b) requires the amendment of Claim 19 to clearly state the limitations for the method of “forming the coplanar upper surfaces of the spacer and the dielectric layer” and how that relates to the forming of “the first electrode of the MIM capacitor”, or an argument against the rejection can be made by providing supporting explanations, see MPEP 2173.02. Claim 20 would then be allowable, as the prior art fails to anticipate or make obvious the method of forming “the first electrode of the MIM capacitor” using “a blanket etching process”.
Pertinent Art
For the benefit of the Applicant, prior art made of record and not relied upon is considered pertinent to applicant's disclosure through some but not all claimed features of the defined invention is cited here: Niebojewski US 2014/0217520 A1 and Lin US 2023/0420493 A1. Niebojewski discloses an air spacer in a structure similar to Cheng, and Lin discloses a MIM capacitor structure with a plurality of electrodes, spacer elements, and conductive vias, but fails to disclose a void.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA N MICKEY whose telephone number is (571)270-3109. The examiner can normally be reached M-F, 8am to 5pm ET.
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/TERESA NICOLE MICKEY/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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