DETAILED ACTION
Response to Amendment
The Applicant’s Amendment, filed 10/30/2025 has been entered. Claims 3-5 and 12-14 have been canceled. Claims 1-2, 6-11, and 15-18 are pending in the Application.
Response to Arguments
Applicant's arguments filed 10/30/2025 with respect to the prior art rejection have been fully considered but they are not persuasive.
Regarding claims 1 and 10, the Applicant argues that the cited art Tabuchi (US Patent No. 10,817,451) fails to teach the amended limitation “the electronic device selectively utilizes an assigned identifier sent from the master device according to the determination result; when the determination result indicates that the time point of pulling down the second signal is earlier than the time point of pulling down the first signal, the electronic device utilizes a default identifier to be the identifier of the electronic device and prevents utilizing the assigned identifier sent from the master device; and when the determination result indicates that the time point of pulling down the first signal is earlier than the time point of pulling down the second signal, the electronic device utilizes the assigned identifier sent from the master device to be the identifier of the electronic device”. The Examiner respectfully disagrees. Tabuchi discloses the first address XX is an initial address in an initial state of the device thus the first address XX is understood as a default address of the device (see col 2 ln 45-47, during an initial state, each sub-circuit 115, 120 may have identical, first addresses (e.g., address XX)). The Examiner further submits that the claims fail to differentiate the claimed default identifier from the initial address disclosed by Tabuchi. Therefore, the cited art discloses the argued limitation as recited in the claims.
Based on the reasoning above, the rejections have been modified to address the amended limitations. Please see below for the detailed rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-11, and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tabuchi et al US Patent No. 10,817,451.
Regarding claim 1, Tabuchi teaches an electronic device (see figures 1 and 2, sub-circuit 120) for performing communication with a master device (master device 105) via a serial communications bus (communication bus 140, 145, see col 2 ln 8-26), comprising:
a clock terminal, configured to receive a first signal from the master device (SCL2 terminal);
a data terminal, configured to receive a second signal from the master device (SDA2 terminal); and
a determination circuit, coupled to the clock terminal and the data terminal (control circuit 130), configured to determine whether a time point of pulling down the first signal is earlier than a time point of pulling down the second signal, in order to generate a determination result (see col 5 ln 1-19, the second sub-circuit 120 and/or the control circuit 130 may then determine or otherwise detect a reverse start condition, also see figure 5 shows the reverse start condition is when the pulling down of SCL2 signal is earlier than the pulling down of the SDA2 signal);
wherein the master device is coupled to multiple slave devices via the serial communications bus, the electronic device represents one of the multiple slave devices (multiple slaves including sub-circuit 115 and 120), and assignment of an identifier of the electronic device is controlled according to the determination result (see col 2 ln 58-67, the second sub-circuit 120 may utilize the reverse connection to change the first address of the second sub-circuit).
the electronic device selectively utilizes an assigned identifier sent from the master device according to the determination result (see col 5 ln 42-64, the host device 105 may communicate with the first interface circuit 125 and change the address of the first interface circuit 125 from the first address XX to a new address, such as address ZZ);
when the determination result indicates that the time point of pulling down the second signal is earlier than the time point of pulling down the first signal, the electronic device utilizes a default identifier to be the identifier of the electronic device (see col 2 ln 45-47, during an initial state, each sub-circuit 115, 120 may have identical, first addresses (e.g., address XX)) and prevents utilizing the assigned identifier sent from the master device (see col 5 ln 1-19, If the reverse start condition is not detected, then the process ends e.g. when pulling down of SDA2 before pulling down of SCL2 as shown in figure 4 normal start condition, new address is not assigned); and
when the determination result indicates that the time point of pulling down the first signal is earlier than the time point of pulling down the second signal, the electronic device utilizes the assigned identifier sent from the master device to be the identifier of the electronic device (see col 2 ln 58-67, the second sub-circuit 120 may utilize the reverse connection to change the first address of the second sub-circuit, also see col 5 ln 42-64, the host device 105 may communicate with the first interface circuit 125 and change the address of the first interface circuit 125 from the first address XX to a new address, such as address ZZ).
Regarding claim 2, Tabuchi further teaches the electronic device has a first candidate identifier and a second candidate identifier, and the electronic device selects one of the first candidate identifier and the second candidate identifier to be the identifier of the electronic device according to the determination result (see col 4 ln 20-27, the host device 105 is configured to recognize each sub-circuit 115, 120 and change the address from the first address XX to a new address (e.g., YY or ZZ) ).
Regarding claim 6, Tabuchi further teaches a switching circuit, configured to selectively switch utilization of the first signal and the second signal according to the determination result (switching circuit 135).
Regarding claim 7, Tabuchi further teaches when the determination result indicates that the time point of pulling down the second signal is earlier than the time point of pulling down the first signal, the switching circuit prevents switching the utilization of the first signal and the second signal, to make the electronic device take the first signal as a clock signal and take the second signal as a data signal (see col 5 ln 1-19, If the reverse start condition is not detected, then the process ends e.g. when pulling down of SDA2 before pulling down of SCL2 as shown in figure 4 normal start condition, no switching is performed).
Regarding claim 8, Tabuchi further teaches when the determination result indicates that the time point of pulling down the first signal is earlier than the time point of pulling down the second signal, the switching circuit switches the utilization of the first signal and the second signal, to make the electronic device take the first signal as a data signal and take the second signal as a clock signal (see col 5 ln 20-41, If the reverse start condition is detected… the first and second switches SW1, SW2 are switched to a second position (315) (such as illustrated in FIG. 2). The second position may be opposite from the first position. For example, the second position may be defined as the first switch SW1 connecting the second clock terminal SCL2 (and the data line 140) to the data terminal of the first interface circuit 125 and the clock terminal of the second interface circuit 200, and the second switch SW2 is connecting the second data terminal SDA2 (and the clock line 145) to the clock terminal of the first interface circuit 125 and the data terminal of the second interface circuit 200).
Regarding claim 9, Tabuchi further teaches the serial communications bus is an inter-integrated circuit (I2C) bus (see col 2 ln 8-26, the system 100 may be configured as an I2C (Inter-integrated Circuit) comprising a serial computer bus).
Regarding claims 10-11, and 15-18, please refer to the rejection of claims 1-2 and 6-9 since the claimed limitation is substantially similar. Claims 10-11 and 15-18 recite the method performed by the electronic device of claims 1-2 and 6-9 addressed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Arnould US 20200409902 discloses replacing default address within the slave integrated circuit
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG H DANG whose telephone number is (571)272-0470. The examiner can normally be reached Monday-Friday 9:30AM - 6:00PM.
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/PHONG H DANG/Primary Examiner, Art Unit 2184