Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in this office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 2, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 7, 9, 11, 16, 17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Daly et al. (U.S. Patent Pub. No. 2017/0180273).
Regarding claims 1 and 11, Daly et al. teaches a method comprising: a storage configured to store instructions (fig. 3, ref. num 301); and a processor configured to execute the instructions and cause the processor to (fig. 3, ref. num 302): based on receiving a first packet within a service for transmitting the first packet to a destination location, processing a first portion of the first packet in a processor based on execution of a first fiber until a first hardware call is reached (abstract, paragraph 0017-0018 and 0063); sending the first packet to a first circuit for processing the first packet based on the first hardware call (paragraph 0069); and processing a portion of a second packet associated with a second fiber while the first packet is processing in the first circuit (paragraph 0065).
Regarding claims 6 and 16, Daly et al. teaches wherein the first hardware call is associated with one of a portion of a regular expression, a pattern matching function, an encryption or decryption, and a compression or decompression (paragraph 0009).
Regarding claims 7 and 17, Daly et al. teaches wherein a second hardware call is different from the first hardware call (paragraph 0051).
Regarding claims 9 and 19, Daly et al. teaches further comprising: polling the first circuit while the first packet is processing in the first circuit; and pausing the processing of the first packet in the first circuit based on a criteria (paragraph 0065-0066).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5, 8, 10, 12-15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Daly et al. (U.S. Patent Pub. No. 20170180273) in view of Guo et al. (U.S. Patent Pub. No. 2023/0289242).
Regarding claims 2 and 12, Daly et al. teaches the limitations of claims 1 and 11, above. However, Daly et al. does not teach further comprising: switching a context of the processor to a second state associated with the second fiber.
Guo et al. teaches further comprising: switching a context of the processor to a second state associated with the second fiber (abstract and paragraph 0158).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine switching a context, as taught by Guo et al., with the method of Daly et al. It would have been obvious for such modifications because the asynchronous transactions ensures the processor remains utilized while waiting for the hardware accelerators of Daly.
Regarding claims 3 and 13, Daly et al. as modified by Guo et al. teaches wherein the second state associated with the second fiber includes values associated with registers of the processor and a stack (see paragraph 0179 of Guo et al.).
Regarding claims 4 and 14, Daly et al. teaches further comprising: after processing the portion of the second packet, switching the context of the processor to a first state associated with the first fiber; processing a second portion of the first packet based on execution of the first fiber until a second hardware call is reached; and sending the first packet for processing the first packet based on the second hardware call (paragraph 0068).
Regarding claims 5 and 15, Daly et al. teaches wherein the second hardware call is associated with a different circuit (paragraph 0051).
Regarding claims 8 and 18, Daly et al. teaches all the limitations of claims 1 and 11, above. However, Daly et al. does not teach further comprising: outputting the first packet from a first stage to a second stage of the service before the second packet, wherein the second packet began processing before the first packet.
Guo et al. teaches further comprising: outputting the first packet from a first stage to a second stage of the service before the second packet, wherein the second packet began processing before the first packet (paragraph 0021).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine outputting packets in different orders, as taught by Guo et al., with the method of Daly et al. It would have been obvious for such modifications because completion of packets out of order can maximize throughput.
Regarding claims 10 and 20, Daly et al. teaches all the limitations of claims 1 and 11, above. However, Daly et al. does not teach wherein processing the portion of the second packet associated with the second fiber comprises: sending the second packet to hardware and associated information to resume processing the second packet in the hardware, wherein the processing is associated with one of a regular expression, a pattern matching function, an encryption or decryption, and a compression or decompression applied to the second packet.
Guo et al. teaches wherein processing the portion of the second packet associated with the second fiber comprises: sending the second packet to hardware and associated information to resume processing the second packet in the hardware, wherein the processing is associated with one of a regular expression, a pattern matching function, an encryption or decryption, and a compression or decompression applied to the second packet (paragraph 0170).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine resume processing, as taught by Guo et al., with the method of Daly et al. It would have been obvious for such modifications because state information provides a way to return to the correct thread of processing.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON HOFFMAN whose telephone number is (571)272-3863. The examiner can normally be reached Monday-Friday 8:30AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Pwu can be reached at (571)272-6798. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON HOFFMAN/Primary Examiner, Art Unit 2433
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