Prosecution Insights
Last updated: August 17, 2026
Application No. 18/624,201

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Non-Final OA §102§112
Filed
Apr 02, 2024
Priority
Sep 04, 2023 — RE 10-2023-0117127
Examiner
PRENTY, MARK V
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
674 granted / 738 resolved
+31.3% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
9 currently pending
Career history
743
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
29.3%
-10.7% vs TC avg
§102
39.5%
-0.5% vs TC avg
§112
21.2%
-18.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 738 resolved cases

Office Action

§102 §112
ANY LISTING OF CLAIMS FILED IN RESPONSE TO THIS OFFICE ACTION SHOULD BE IN BLACK INK ONLY. CLAIM AMENDMENTS SHOULD NOT BE MADE IN RED OR YELLOW INK. Claim 15 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Specifically, dependent claim 15 recites “the corner portion defines an air gap,” which is inconsistent with independent claim 11’s “a corner portion of the gate insulating layer fills the first recess region.” Claims 11 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (United States Patent Application Publication 2022/0285533 cited in the Information Disclosure Statement filed on April 2, 2024). As to independent claim 11, Lee discloses a semiconductor device (see the entire reference, including the Figs. 9, 10B, 11B and 12 disclosure), comprising: a substrate 304 including an active pattern; a channel pattern on the active pattern, the channel pattern including a first semiconductor pattern 310 and a second semiconductor pattern 310, which are stacked to be spaced apart from each other; a source/drain pattern 802 connected to the first and second semiconductor patterns; a gate electrode 1104 on the channel pattern, the gate electrode including an inner electrode interposed between the first and second semiconductor patterns; and a gate insulating layer 1102 between the first and second semiconductor patterns and the inner electrode, wherein an inner region 902 is defined between the first and second semiconductor patterns and the source/drain pattern, the inner region 902 includes a first recess region 1105 formed in a corner thereof, the first recess region is recessed in a direction away from the inner electrode, the gate insulating layer 1102 is provided to cover an inner surface of the inner region, and a corner portion of the gate insulating layer 1102 fills the first recess region 1105 (page 8, paragraph [0051]). As to dependent claim 14, Lee’s inner region 902 further comprises: a second recess region, which is recessed toward the second semiconductor pattern (Fig. 9B), the second semiconductor pattern 310 includes a bottom surface defined by the second recess region, and the bottom surface is higher than the corner portion. Claims 12 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the independent claim and any intervening claims. Claims 1-10 and 16-20 are allowed. The prior art does not disclose or suggest independent claims 1 and 16 as a whole. ANY LISTING OF CLAIMS FILED IN RESPONSE TO THIS OFFICE ACTION SHOULD BE IN BLACK INK ONLY. CLAIM AMENDMENTS SHOULD NOT BE MADE IN RED OR YELLOW INK. Registered practitioners can telephone the examiner at (571) 272-1843. Any voicemail message left for the examiner should include the registration number of the registered practitioner calling. The examiner’s supervisor is Wael Fahmy, whose telephone number is (571) 272-1705. /MARK V PRENTY/Primary Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Apr 02, 2024
Application Filed
Aug 06, 2026
Examiner Interview Summary
Aug 06, 2026
Non-Final Rejection mailed — §102, §112
Aug 06, 2026
Examiner Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707900
RESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
3y 7m to grant Granted Aug 11, 2026
Patent 12707902
RESISTIVE RANDOM-ACCESS MEMORY DEVICE
2y 3m to grant Granted Aug 11, 2026
Patent 12701718
SEMICONDUCTOR DEVICE
3y 8m to grant Granted Aug 04, 2026
Patent 12685034
ATOMICALLY TUNED ULTRATHIN MEMRISTORS
2y 10m to grant Granted Jul 14, 2026
Patent 12684787
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
2y 10m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.1%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 738 resolved cases by this examiner. Grant probability derived from career allowance rate.

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