DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki et al (Yamasaki, Nobuyuki, Ikuo Magaki, and Tsutomu Itou. "Prioritized SMT architecture with IPC control method for real-time processing." 13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07). IEEE, 2007) (hereinafter Yamasaki) in view of Dean et al (Dean, Jeffrey, and Sanjay Ghemawat. "MapReduce: simplified data processing on large clusters." Communications of the ACM 51.1 (2008): 107-113) (hereinafter Dean).
As per claim 1, Yamasaki teaches:
An in-vehicle device configured to execute one process in a plurality of threads (Yamasaki, 1 Introduction—under BRI, a plurality of threads can be eight threads).
Yamasaki does not expressly teach:
wherein the process is configured to execute N tasks that are at least three tasks, and process the N tasks in a plurality of threads fewer than the N tasks.
However, Dean discloses:
wherein the process is configured to execute N tasks that are at least three tasks (Dean, Fig. 1 Execution overview--under BRI, N tasks can be Split 0-4), and process the N tasks in a plurality of threads fewer than the N tasks (Dean, Fig 1 Execution overview--under BRI, a plurality of threads fewer than the N tasks can be 3 workers in map phase) .
Both Dean and Yamasaki pertain to the art of parallel processing.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Dean’s method to execute N tasks that are at least three tasks, and process the N tasks in a plurality of threads fewer than the N tasks because task numbers are variable. A system needs to be able to handle arbitrary number of tasks to be useful.
As per claim 2, Yamasaki/Dean teaches:
The in-vehicle device according to claim 1 (see rejection on claim 1), wherein a plurality of simultaneously processible first tasks among the N tasks is processed in different threads (Dean, Fig. 1 Execution overview--under BRI, first tasks can be Split 0 and 2).
As per claim 3, Yamasaki/Dean teaches:
The in-vehicle device according to claim 1 (see rejection on claim 1), wherein the process is configured to process a plurality of second tasks to be sequentially processed among the N tasks in the same thread (Dean, Fig. 1 Execution overview--under BRI, second tasks can be Split 0 and 1 and sequentially can be together [ a synonym according to Merriam Webster).
As per claim 5, see rejection on claim 1.
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki/Dean as applied to claim 1 above, and further in view of Ross et al ( US 8806507) (hereinafter Ross).
As per claim 4, Yamasaki/Dean teaches:
The in-vehicle device according to claim 1 (see rejection on claim 1).
Yamasaki/Dean does not expressly each:
wherein the process is configured to perform thread-to-thread communication one time or more, and N-2 times or less while executing the N tasks.
However, Ross discloses:
wherein the process is configured to perform thread-to-thread communication one time or more (Ross, Fig 1 ), and N-2 times or less while executing the N tasks (Ross, Fig 1—under BRI, N-2 can be any number minus 2 including infinity minus 2).
Both Ross and Yamasaki/Dean pertain to the art of parallel processing.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Dean’s method perform thread-to-thread communication one time or more, and N-2 times or less while executing the N tasks because thread numbers are variable. A system needs to be able to handle arbitrary number of threads to be useful.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2021/0234855 teaches a method for communicating between threads in message queues.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
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/CHARLIE SUN/Primary Examiner, Art Unit 2198
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