DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 11/21/2025 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 2 recites the broad recitation “the average thickness of the sintered silver layer is less than or equal to 1 µm and the claim also recites the average thickness of the sintered silver layer is between 100 nm and 1000 nm” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 3 recites the broad recitation “the average thickness of the sintered silver layer is less than or equal to 1 µm and the claim also recites the average thickness of the sintered silver layer is between 100 nm and 1000 nm” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 10 recites the broad recitation “the average thickness of the sintered silver layer is less than or equal to 1 µm and the claim also recites the average thickness of the sintered silver layer is between 100 nm and 1000 nm” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-6, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Matsuoka (US 2011/0261505).
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Regarding claim 1, Matsuoka discloses in fig. 5A-5D, a capacitor assembly package structure (200), comprising:
a capacitor assembly (50) including a plurality of capacitor structures (20) that are stacked in sequence and electrically connected to each other, wherein each of the capacitor structures (20) has a positive electrode portion (21) and a negative electrode portion (24, 27, 28);
an insulating package body (29) configured to encapsulate a plurality of the capacitor structures (20); and
an electrode assembly (25, 26) including a first electrode structure (25) and a second electrode structure (26), wherein the first electrode structure (25) and the insulating package body (29) cooperate with each other and are electrically connected to the positive electrode portion (21) of the capacitor structure (20), and the second electrode structure (26) and the insulating package body (29) cooperate with each other and are electrically connected to the negative electrode portion (24, 27, 28) of the capacitor structure (20);
wherein each of the capacitor structures (20) includes a sintered silver layer (27, 28), and the sintered silver layer (27, 28) includes more than 95% pure silver material [0090], [0103].
Matsuoka discloses the sintered silver layer includes 90 % by mass or more of pure silver [0090].
Matsuoka does not have a specific example where the sintered silver layer includes more than 95 % pure silver material.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Regarding claim 4, Matsuoka discloses a capacitor structure (20) configured to be applied to a capacitor assembly package structure, wherein the capacitor structure comprises a sintered silver layer [0090], [0109], and the sintered silver layer includes more than 95% pure silver material [0090], [0109].
Matsuoka discloses the sintered silver layer includes 90 % by mass or more of pure silver [0090].
Matsuoka does not have a specific example where the sintered silver layer includes more than 95 % pure silver material.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Regarding claim 5, Matsuoka discloses the capacitor structure (20) includes a metal foil [0085], an insulating surrounding layer [0085] disposed around a first portion of the metal foil [0085], a conductive polymer layer [0007], [0030], [0085] for covering the first portion of the metal foil and contacting the insulating surrounding layer [0085] and a carbon glue layer [0031], [0085] for covering the conductive polymer layer [0007], [0030], [0085], and contacting the insulating surrounding layer [0085], and the sintered silver layer (27, 28) is configured for covering the carbon glue layer [0085] and contacting (at least indirectly) the insulating surrounding layer [0085];
wherein the sintered silver layer is an outermost layer (see fig. 5A) of the capacitor structure (20);
wherein a second portion of the metal foil [0085] of the capacitor structure (20) is not covered (@ 25) by the insulating surrounding layer [0085].
Regarding claim 6, Matsuoka discloses the capacitor structure (20) includes a metal foil [0085], an insulating surrounding layer [0085] disposed around a first portion of the metal foil and a conductive polymer layer [0007], [0030] [0085] for covering the first portion of the metal foil [0085] and contacting the insulating surrounding layer [0085], and the sintered silver layer (27, 28) is configured for covering the conductive polymer layer [0085] and contacting (at least indirectly) the insulating surrounding layer [0085]; wherein the sintered silver layer (27, 28) is an outermost layer of the capacitor structure; wherein a second portion of the metal foil [0085] of the capacitor structure is not covered (@ 25) by the insulating surrounding layer [0085].
Regarding claim 9, Matsuoka discloses an electronic device configured to use a capacitor assembly package structure, characterized in that the capacitor assembly package structure (200) comprises: a capacitor assembly (200) including a plurality of capacitor structures (20) that are stacked in sequence and electrically connected to each other, wherein each of the capacitor structures (20) has a positive electrode portion (21) and a negative electrode portion (24);
an insulating package body (29) configured to encapsulate a plurality of the capacitor structures; and
an electrode assembly (25, 26) including a first electrode structure (25) and a second electrode (26) structure, wherein the first electrode structure (25) and the insulating package body (29) cooperate with each other and are electrically connected to the positive electrode portion (21) of the capacitor structure (20), and the second electrode structure (26) and the insulating package body (29) cooperate with each other and are electrically connected to the negative electrode portion (24) of the capacitor structure (20); wherein
each of the capacitor structures includes a sintered silver layer, and the sintered silver layer includes more than 95% pure silver material [0090], [0103].
Matsuoka discloses the sintered silver layer includes 90 % by mass or more of pure silver [0090].
Matsuoka does not have a specific example where the sintered silver layer includes more than 95 % pure silver material.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US 2013/0258555) in view of Petrzilek et al. (US 2017/0338046).
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Regarding claim 1, Chiu et al. disclose in Fig. 3-5, a capacitor assembly package structure (Fig. 3), comprising:
a capacitor assembly including a plurality of capacitor structures (1) that are stacked in sequence and electrically connected to each other, wherein each of the capacitor structures (1) has a positive electrode portion (11) and a negative electrode portion (12);
an insulating package body (4) configured to encapsulate a plurality of the capacitor structures (1); and
an electrode assembly (3A, 3B) including a first electrode structure (3A) and a second electrode structure (3B), wherein the first electrode structure (3A) and the insulating package body (4) cooperate with each other and are electrically connected to the positive electrode portion (11) of the capacitor structure (1), and the second electrode structure (3B) and the insulating package body (4) cooperate with each other and are electrically connected to the negative electrode portion (12) of the capacitor structure (1);
wherein each of the capacitor structures (1) includes a cathode outer layer (122, 123).
Chiu et al. disclose the claimed invention except for the outer cathode layer comprises a sintered silver layer, wherein the sintered silver layer includes more than 95% pure silver material.
Petrzilek et al. disclose an improved outer cathode layer, where the outer cathode layer comprises a sintered silver layer, wherein the sintered metal layer includes more than 95% pure silver material [0052].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor assembly package of Chiu et al. so that the outer cathode layer includes a sintered silver layer, wherein the sintered metal layer includes more than 95% pure silver material, since such a modification would form a capacitor assembly package structure that exhibits good properties at high temperatures (mechanically stable).
Regarding claim 2, Chiu et al. disclose each of the capacitor structures (1) includes a metal foil (111 – [0022]), an insulating surrounding layer (112) disposed around a first portion of the metal foil (111), a conductive polymer layer (121 – [0023]) for covering the first portion of the metal foil (111) and contacting the insulating surrounding layer (112) and a carbon glue layer (122 – [0023]) for covering the conductive polymer layer (121) and contacting the insulating surrounding layer (122), and the sintered silver layer (123 – Petrzilek et al.) configured for covering the carbon glue layer (122) and contacting the insulating surrounding layer (4);
wherein the sintered silver layer (123) is an outermost layer of the capacitor structure (1), and the two sintered silver layers (123) of two adjacent ones of the capacitor structures (1) are electrically connected to each other through a conductive material (2 – [0026]);
wherein a second portion of the metal foil (111) of each of the capacitor structures (1) is not covered by the insulating surrounding layer (112), and the second portions of the metal foils of the capacitor structures (1) are stacked in sequence or separate from each other;
wherein an average thickness of the sintered silver layer is less than or equal to 1 um, and a resistivity of the sintered silver layer is less than a resistivity of a silver glue material formed by mixing epoxy resin and silver powder;
wherein the average thickness of the sintered silver layer is between 100 nm and 1000 nm, and the resistivity of the sintered silver layer is between 1x10-5 Ωcm and 1x10-6 Ωcm, to reduce or maintain an equivalent series resistance of the capacitor assembly package structure;
wherein the electrode assembly is a conductive pin assembly (Fig. 3),
when the electrode assembly is the conductive pin assembly (Fig. 3), the first electrode structure (3A) of the electrode assembly (3A, 3B) includes a first embedded portion (3A) covered by the insulating package body (4) and a first exposed portion (see annotated Fig. 3 below) connected to the first embedded portion and exposed from the insulating package body (see annotated Fig. 3 below), the first embedded portion of the first electrode structure is electrically connected to the positive electrode portion (11) of the capacitor structure (1), and the first exposed portion of the first electrode structure extends along an outer surface of the insulating package body (4); wherein,
when the electrode assembly is the conductive pin assembly, the second electrode structure (3B) of the electrode assembly (3A, 3B) includes a second embedded portion (see annotated Fig. 3 below) covered by the insulating package body (4) and a second exposed portion (see annotated Fig. 3 below) connected to the second embedded portion and exposed from the insulating package body (3B), the second embedded portion of the second electrode structure is electrically connected to the negative electrode portion (12) of the capacitor structure (1), and the second exposed portion of the second electrode structure extends along the outer surface of the insulating package body (4).
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Regarding claim 3, the modified Chiu et al. disclose each of the capacitor structures (1) includes a metal foil (111, [0022]), an insulating surrounding layer (112) disposed around a first portion of the metal foil (111) and a conductive polymer layer (121, [0023]) for covering the first portion of the metal foil (111) and contacting the insulating surrounding layer (121), and the sintered silver layer (Petrzilek et al., [0052]) configured for covering the conductive polymer layer (121) and contacting (at least indirectly) the insulating surrounding layer (121); wherein
the sintered silver layer (Petrzilek et al., [0052]) is an outermost layer of the capacitor structure (1), and the two sintered silver layers (Petrzilek et al., [0052]) of two adjacent ones of the capacitor structures (1) are electrically connected to each other through a conductive material (2); wherein
a second portion of the metal foil (111) of each of the capacitor structures is not covered by the insulating surrounding layer (112 – at connection portion), and the second portions of the metal foils (111) of the capacitor structures are stacked in sequence (Fig. 3) or separate from each other; wherein
an average thickness of the sintered silver layer is less than or equal to 1 µm [0051], and a resistivity of the sintered silver layer is less than a resistivity of a silver glue material formed by mixing epoxy resin and silver powder; wherein
the average thickness of the sintered silver layer is between 100 nm and 1000 nm (Petrzilek et al., [0051]), and the resistivity of the sintered silver layer is between 1x10-5 Ω cm and 1x10-6 Ω cm, to reduce or maintain an equivalent series resistance of the capacitor assembly package structure;
wherein the electrode assembly (3A, 3B) is a conductive pin assembly (Fig. 3); wherein, when the electrode assembly is the conductive pin assembly, the first electrode structure of the electrode assembly includes a first embedded portion covered by the insulating package body (4) and a first exposed portion connected to the first embedded portion and exposed from the insulating package body, the first embedded portion of the first electrode structure is electrically connected to the positive electrode portion of the capacitor structure, and the first exposed portion of the first electrode structure extends along an outer surface of the insulating package body (4, see annotated Fig. 3 below); wherein,
when the electrode assembly is the conductive pin assembly, the second electrode structure of the electrode assembly includes a second embedded portion covered by the insulating package body and a second exposed portion connected to the second embedded portion and exposed from the insulating package body, the second embedded portion of the second electrode structure is electrically connected to the negative electrode portion of the capacitor structure, and the second exposed portion of the second electrode structure extends along the outer surface of the insulating package body (4, see annotated Fig. 3 below).
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While the modified Chiu et al. do not specifically state that “a resistivity of the sintered silver layer is less than a resistivity of a silver glue material formed by mixing epoxy resin and silver powder; wherein the average thickness of the sintered silver layer is between 100 nm and 1000 nm, and the resistivity of the sintered silver layer is between 1x10-5 Ωcm and 1x10-6 Ωcm, to reduce or maintain an equivalent series resistance of the capacitor assembly package structure” it is understood to be an inherent feature. When the structure recited in the references is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent.
Regarding claim 9, Chiu et al. disclose an electronic device configured to use a capacitor assembly package structure (Fig. 3-5), characterized in that the capacitor assembly package structure comprises: a capacitor assembly including a plurality of capacitor structures (1) that are stacked in sequence and electrically connected to each other, wherein each of the capacitor structures has a positive electrode portion (11) and a negative electrode portion (12);
an insulating package body (4) configured to encapsulate a plurality of the capacitor structures (1); and
an electrode assembly (3A, 3B) including a first electrode structure (3A) and a second electrode structure (3B), wherein the first electrode structure (3A) and the insulating package body (4) cooperate with each other and are electrically connected to the positive electrode portion (11) of the capacitor structure, and the second electrode structure (3B) and the insulating package body (4) cooperate with each other and are electrically connected to the negative electrode portion (12) of the capacitor structure (1);
wherein each of the capacitor structures (1) includes a cathode outer layer (122, 123).
Chiu et al. disclose the claimed invention except for the outer cathode layer comprises a sintered silver layer, wherein the sintered silver layer includes more than 95% pure silver material.
Petrzilek et al. disclose an improved outer cathode layer, where the outer cathode layer comprises a sintered silver layer, wherein the sintered metal layer includes more than 95% pure silver material [0052].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor assembly package of Chiu et al. so that the outer cathode layer includes a sintered silver layer, wherein the sintered metal layer includes more than 95% pure silver material, since such a modification would form a capacitor assembly package structure that exhibits good properties at high temperatures (mechanically stable).
Regarding claim 10, the modified Chiu et al. disclose each of the capacitor structures includes a metal foil (111), an insulating surrounding layer (112) disposed around a first portion of the metal foil (111) and a conductive polymer layer (121) for covering the first portion of the metal foil (111) and contacting the insulating surrounding layer (112), and the sintered silver layer (Petrzilek et al. – [0052]) is configured for covering the conductive polymer layer (121) and contacting the insulating surrounding layer (112); wherein
the sintered silver layer (Petrzilek et al. – [0052]) is an outermost layer of the capacitor structure (1), and the two sintered silver layers (Petrzilek et al.) of two adjacent ones of the capacitor structures (1) are electrically connected to each other through a conductive material (2); wherein a second portion of the metal foil (111) of each of the capacitor structures is not covered by the insulating surrounding layer (at least @ 3A, 112), and the second portions of the metal foils (111) of the capacitor structures (1) are stacked in sequence or separate from each other (Fig. 3); wherein
an average thickness of the sintered silver layer is less than or equal to 1 µm [0051], and a resistivity of the sintered silver layer is less than a resistivity of a silver glue material formed by mixing epoxy resin and silver powder; wherein
the average thickness of the sintered silver layer is between 100 nm and 1000 nm [0051], and the resistivity of the sintered silver layer is between 1x10-5 Ω cm and 1x10-6 Ω cm, to reduce or maintain an equivalent series resistance of the capacitor assembly package structure.
While the modified Chiu et al. do not specifically state that “a resistivity of the sintered silver layer is less than a resistivity of a silver glue material formed by mixing epoxy resin and silver powder; wherein the average thickness of the sintered silver layer is between 100 nm and 1000 nm, and the resistivity of the sintered silver layer is between 1x10-5 Ωcm and 1x10-6 Ωcm, to reduce or maintain an equivalent series resistance of the capacitor assembly package structure” it is understood to be an inherent feature. When the structure recited in the references is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2016/0027588
US 2008/0106852
JP 2004088073
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/ERIC W THOMAS/Primary Examiner, Art Unit 2848
ERIC THOMAS
Primary Examiner
Art Unit 2848