DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 02/09/2026. Claim 1-3 and 8-9 have been amended. Claims 1-20 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application, 17/463,397 filed on 08/31/2021, under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the Examiner’s response set forth below.
(1)Applicant contends that, regarding claim 1, “there is no motivation to modify Gibbons with Floman and/or Bode to provide an external user interface for per-partition thresholds than to block writes to that partition at threshold – indeed, the prior art teaches away by favoring endurance-preserving relocation over denial”. The Examiner respectfully disagrees.
As set forth in the MPEP, a reference teaches away only when it “criticize, discredit, or otherwise discourage” the claimed solution. The MPEP further clarifies that “the prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed….”. Neither Floman nor Bode criticizes, discredits or otherwise discourages the claimed limitations, therefore, the cited prior art does not teach away from the claimed invention.
(2)The rest of Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(3) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 9, 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanno (US2018/0173430), hereinafter Kanno in view of Floman et al. (US 2014/0181382), hereinafter Floman, and further in view of Bode et al. (US 2021/0263655), hereinafter Bode.
Regarding claim 1, Kanno teaches a device, comprising:
at least one memory cell (Kanno, [0038], The NAND flash memory 5 includes a memory cell array having a plurality of memory cells arranged in a matrix);
circuitry (Kanno, [0060], CPU 12) configured to:
present, via an interface, an option to control writes to a partition associated with the at least one memory cell;
receive, via the interface, a write threshold for the partition, wherein the write threshold is established based on selection of the option and the partition being identified as write-intensive;
monitor an indication of an accumulated amount of data written into the partition (Kanno, [0078], The total-amount-of-written-data measurement unit 22 measures a total amount of data written into each VSSD, i.e., a cumulative total amount of data that have been written into each VSSD); and
block, in response to the accumulated amount of data reaching the write threshold, at least one write request to the partition (Kanno, [0062], The write command requests the SSD 3 to write data designated by the write command. The write command may include a start LBA, a transfer length, and a VSSD ID; [0205], In a case where the measured value of the total write amount of the VSSD 51 (i.e., VSSD #1) reaches the upper limit value of the total write amount for the VSSD 51 (i.e., VSSD #1) (YES in Step S301), the write limitation unit 23 limits writing of data into the VSSD 51 from the host 2 (Step S302). In Step S302, the write limitation unit 23 may prohibit writing of data into the VSSD 51 (i.e., VSSD #1) from the host 2; [0248]).
Kanno does not explicitly teach present, via an interface, an option to control writes to a partition associated with the at least one memory cell; receive, via the interface, a write threshold for the partition, wherein the write threshold is established based on selection of the option and the partition being identified as write-intensive, as claimed.
However, Kanno in view of Floman teaches present, via an interface, an option to control writes to a partition associated with the at least one memory cell (Floman, [0086], FIG. 5 illustrates a user interface for receiving a memory configuration selection of an exemplary embodiment in accordance with this invention. User interface (UI) 510 displays a number of options 520 that the user may select; Fig.5);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kanno to incorporate teachings of Floman to allow storage memory used in I/O operations to be configured via an interface. A person of ordinary skill in the art would have been motivated to combine the teachings of Kanno with Floman because it improves efficiency of the storage system disclosed in Kanno by configuring storage partitions based on user selections.
The combination of Kanno does not explicitly teach receive, via the interface, a write threshold for the partition, wherein the write threshold is established based on selection of the option and the partition being identified as write-intensive, as claimed.
However, the combination of Kanno in view of Bode teaches receive, via the interface (Bode, Fig.2, Note - the component in storage management system that receives the command is an interface), a write threshold for the partition, wherein the write threshold is established based on selection of the option and the partition being identified as write-intensive (Bode, [0081]-[0083]; [0084], the process can be implemented in storage manager 216 in computer system 218 in FIG. 2; [0085], The process begins by receiving a request to create a new logical unit number (LUN) for a volume in a storage system (step 600); [0086], The process receives an expected write level for the new logical unit number (step 602). In step 602, the write level can be the amount of data expected to be written to the logical unit number on a daily basis; [0087]; Kanno, [0062]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Kanno to incorporate teachings of Bode to receive a write level threshold when creating a partition in a tiered solid state drive after making a selection on the UI (in Floman). Accordingly, a virtual SSD (VSSD in Kanno) that exceeds a write level threshold can be identified as write-intensive. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Kanno with Bode because it improves flexibility of the storage system disclosed in the combination of Kanno by allowing user to configure a storage partition based on user’s input.
Regarding claim 2, the combination of Kanno teaches all the features with respect to claim 1 as outlined above. The combination of Kanno further teaches the device of claim 1, wherein the circuitry is further configured to: allow the data for write request to be written into the partition associated with the at least one memory cell based on the write count being below the write threshold (Kanno, [0063], When the controller 4 receives a write command including a certain virtual machine ID, the controller 4 writes data into the VSSD associated with the virtual machine ID; ).
Regarding claim 9, the combination of Kanno teaches all the features with respect to claim 1 as outlined above. The combination of Kanno further teaches the device of claim 1, wherein the circuitry is further configured to: convert, based on an address map, a logical address associated with the write request referencing the partition into a physical address of the at least one memory cell (Kanno, [0047]-[0049]; [0050], the controller 4 uses a plurality of lookup tables (LUTs) 31C, 32C, . . . , and 37C, which respectively correspond to a plurality of virtual SSDs (VSSD # 1, VSSD # 2, . . . , and VSSD #n), to manage mapping between respective LBAs and physical addresses of respective virtual SSDs (VSSDs)).
Regarding claim 10, the combination of Kanno teaches all the features with respect to claim 1 as outlined above. The combination of Kanno further teaches the device of claim 1, wherein the circuitry is further configured to: receive a modified write threshold for the partition via the interface; and control writing of the data to the partition based on the modified write threshold (Kanno, [0086], An end user corresponding to the virtual machine which uses the VSSD # 1 may request the data center operator to increase the total amount of writable data. The data center operator may charge an extra usage charge to the end user and may transmit a VSSD management command, which is for resetting the VSSD # 1 such that the total amount of data capable of being written into the VSSD # 1 is increased, to the SSD 3)
Regarding claim 11, the combination of Kanno teaches all the features with respect to claim 1 as outlined above. The combination of Kanno further teaches the device of claim 1, wherein the circuitry is further configured to: set a threshold for a specified number of program erase cycles for a memory cell of the at least one memory cell that is associated with the partition (Kanno, [0072]; Floman, [0081]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kanno to incorporate teachings of Floman to allow storage memory used in I/O operations to be configured via an interface and obtains maximum P/E counts for memory associated with the configured storage memory. A person of ordinary skill in the art would have been motivated to combine the teachings of Kanno with Floman because it improves efficiency of the storage system disclosed in Kanno by balancing reliability and density of the storage system.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kanno, Floman, and Bode as applied to claim 1 above, and further in view of Qawami (US 2020/0151052), hereinafter Qawami.
Regarding claim 3, the combination of Kanno teaches all the features with respect to claim 1 as outlined above. The combination of Kanno does not explicitly teach the device of claim 1, wherein the circuitry is further configured to: transmit, based on the accumulated amount satisfying the write threshold, a notification via the interface to indicate that the write threshold has been reached, as claimed.
However, the combination of Kanno in view of Qawami teaches the device of claim 1, wherein the circuitry is further configured to: transmit, based on the accumulated amount satisfying the write threshold, a notification via the interface to indicate that the write threshold has been reached (Qawami, [0031], when memory device 230 is a selected device to manage a write count for a group of memory devices, alert 246 enables the selected device to send an alert in response to a write count reaching a threshold; Kanno, [0192], The counter 61 counts an amount of data written into the VSSD 51 (i.e., VSSD #1) ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Kanno to incorporate teachings of Qawami to include an alert interface 246 to transmit an alert via the alert interface in response to a write count reaching a threshold. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Kanno with Qawami because it improves communication of the storage system disclosed in the combination of Kanno by providing feedback information via interfaces to indicate processing criteria have been met.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kanno, Floman, Bode, and Qawami as applied to claim 3 above, and further in view of Masuo et al. (US 2021/0117317), hereinafter Masuo.
Regarding claim 4, the combination of Kanno teaches all the features with respect to claim 3 as outlined above. The combination of Kanno does not explicitly teach the device of claim 3, wherein the circuitry is further configured to: determine a type of function to prioritize over at least one other type of function to utilized for a remaining amount of memory cells of the at least one memory cell of the partition, as claimed.
However, the combination of Kanno in view of Masuo teaches the device of claim 3, wherein the circuitry is further configured to: determine a type of function to prioritize over at least one other type of function to utilized for a remaining amount of memory cells of the at least one memory cell of the partition (Masuo, [0064], In the second state in which the data writable capacity is less than the threshold value “Thresh_1” (i.e., K<“Thresh_1”), the prevention of a failure of the device (i.e., the SSD, which is the memory system 1) should be prioritized over the stabilization of the performance … In this situation, the ordinary gear ratio calculator 1231 calculates that the gear ratio is “0:X”, and thus, the memory system 1 stops host write and prioritizes GC write; claim 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Kanno to incorporate teachings of Masuo to prioritize garbage collection over host write when writable capacity is less than a threshold. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Kanno with Masuo because it improves reliability of the storage system disclosed in the combination of Kanno by ensuring the prevention of a failure of a storage device is prioritized over the stabilization of the performance of the storage device (Masuo, [0064]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kanno, Floman, and Bode as applied to claim 1 above, and further in view of Gibbons et al. (US 9,418,699), hereinafter Gibbons.
Regarding claim 5, the combination of Kanno teaches all the features with respect to claim 1 as outlined above. The combination of Kanno does not explicitly teach the device of claim 1, further comprising an integrated circuit die on which the at least one memory cell is formed, as claimed.
However, the combination of Kanno in view of Gibbons teaches the device of claim 1, further comprising an integrated circuit die on which the at least one memory cell is formed (Gibbons, col.4, lines 36-49, it is understood that solid-state memory may comprise one or more of various types of memory devices such as flash integrated circuits).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Kanno to incorporate teachings of Gibbons to include a flash integrated circuits containing as array of memory cells. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Kanno with Gibbons because it improves efficiency and performance of the storage system disclosed in the combination of Kanno by providing high storage density and reduced processing latency.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kanno, Floman, and Bode as applied to claim 1 above, and further in view of Kim et al. (US 9,785,550), hereinafter Kim.
Regarding claim 6, the combination of Kanno teaches all the features with respect to claim 1 as outlined above. The combination of Kanno does not explicitly teach the device of claim 1, wherein the circuitry is further configured to: perform wear leveling across the partition and at least one other partition associated with the at least one memory cell, as claimed.
However, the combination of Kanno in view of Kim teaches the device of claim 1, wherein the circuitry is further configured to: perform wear leveling across the partition and at least one other partition associated with the at least one memory cell (Kim, col.7. lines 41-43, At the step S340, the controller 100 may perform a wear leveling operation on the memory areas AR1 to AR4.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Kanno to incorporate teachings of Kim to perform a wear leveling operation on memory areas in response to one or more statistic triggers. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Kanno with Kim because it improves efficiency of the storage system disclosed in the combination of Kanno by performing wear leveling on the storage system in order to extend lifetime of nonvolatile memory devices (Kim, col.6, lines 38-43).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kanno, Floman, and Bode as applied to claim 1 above, and further in view of Buchheit (US2011/0251987), hereinafter Buchheit.
Regarding claim 7, the combination of Kanno teaches all the features with respect to claim 1 as outlined above. The combination of Kanno does not explicitly teach the device of claim 1, wherein the circuitry is further configured to: conduct a time shift operation during play back of streaming content based on data buffered in the partition, as claimed.
However, the combination of Kanno in view of Buchheit teaches the device of claim 1, wherein the circuitry is further configured to: conduct a time shift operation during play back of streaming content based on data buffered in the partition (Buchheit, [0047], Engine 332 can utilize streaming queue 336 to perform time-shifting of a content streaming request. Engine 332 can process streaming queue 336 for a pending content streaming request and communicate a content streaming request to content server 310. Once the content streaming request has been communicated, the engine 332 can update streaming queue 336 to reflect the current state of the content streaming request…. Engine 336 can continuously update streaming queue 336 based on received content 312; Fig. 6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Kanno to incorporate teachings of Buchheit to implement a time-shifting content streaming technique by writing contents of a streaming request to a logical partition when resources are available. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Kanno with Buchheit because it improves efficiency and usability of the storage system disclosed in the combination of Kanno by establishing thresholds for memory space available for the “pre-streaming” of media content (Buchheit, [0017]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kanno, Floman, Bode, and Buchheit as applied to claim 7 above, and further in view of Swanson et al. (US 2016/0092353), hereinafter Swanson.
Regarding claim 8, the combination of Kanno teaches all the features with respect to claim 7 as outlined above. The combination of Kanno does not explicitly teach the device of claim 7, wherein the circuitry is further configured to: disable the time shift operation when the accumulated amount satisfies the write threshold.
However, the combination of Kanno in view of Swanson teaches the device of claim 7, wherein the circuitry is further configured to: disable the time shift operation when the accumulated amount satisfies the write threshold (Kanno, [0192], The counter 61 counts an amount of data written into the VSSD 51 (i.e., VSSD #1); Swanson, [0009], a pending write operation 10 is directed to a target memory region 12 … the target memory region 12 is degraded due to, for example, aging and/or a relatively high number of write operations (e.g., “writes”) being performed on the target memory region 12 over time … Rather than continuing to write data to the target memory region 12 once it has reached the degraded or partially degraded state, the illustrated memory controller 14 … and/or re-directs the pending write operation 10 to a replacement memory region 18; [0017]-[0019]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Kanno to incorporate teachings of Swanson to restrict writing to a degraded memory region (i.e. logical unit) when a target memory region of a pending write operation exceeds an accumulated write data threshold and has transitioned to a degraded memory region. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Kanno with Swanson because it improve efficiency of the storage system disclosed in the combination of Kanno by providing a flexible cold storage pool that grows in capacity as memory ages, wherein the cold storage pool may be used to store large amounts of infrequently changing data in order to extend life of non-volatile memory devices (Swanson, [0009]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kanno, Floman, and Bode as applied to claim 1 above, and further in view of Kiyozaki et al. (US 2021/0035574), hereinafter Kiyozaki.
Regarding claim 12, the combination of Kanno teaches all the features with respect to claim 1 as outlined above. The combination of Kanno does not explicitly teach the device of claim 1, wherein the circuitry is further configured to: provide, via the interface, an option to set the write threshold as a one-time configurable option.
However, the combination of Kanno in view of Hall teaches the device of claim 1, wherein the circuitry is further configured to: provide, via the interface, an option to set the write threshold as a one-time configurable option (Kiyozaki, [0039], the threshold signal THRESH may be configured once … a manufacturer, fabricator, or end user may use a software interface on a computer or a mobile application to reconfigure the threshold signal THRESH).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Kanno to incorporate teachings of Kiyozaki to provide an option of reconfiguring a threshold only once using an interface. A person of ordinary skill in the art would have been motivated to combine the teachings of Kanno with Kiyozaki because it improves flexibility of the storage system disclosed in the combination of Kanno by allowing threshold values to be updated once if needed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NANCI N WONG whose telephone number is (571)272-4117. The examiner can normally be reached Monday-Friday 9am -6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NANCI N WONG/Primary Examiner, Art Unit 2137
Prosecution Insights