Prosecution Insights
Last updated: April 19, 2026
Application No. 18/624,608

LIGHT-EMITTING DEVICE

Final Rejection §103§112
Filed
Apr 02, 2024
Examiner
FARAGALLA, MICHAEL A
Art Unit
2624
Tech Center
2600 — Communications
Assignee
Innolux Corporation
OA Round
4 (Final)
85%
Grant Probability
Favorable
5-6
OA Rounds
3y 0m
To Grant
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
845 granted / 991 resolved
+23.3% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
34 currently pending
Career history
1025
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
66.0%
+26.0% vs TC avg
§102
11.9%
-28.1% vs TC avg
§112
11.2%
-28.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 991 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is in response to the amendment filed by Applicant on 11/05/2025. This action is made FINAL. Examiner’s Notes The only recess mentioned in the instant application is recess 126. The term “adhesive” I only mentioned one time in paragraph 104. It is hereby indicated that the Applicant overcomes the 112(a) rejection regarding the term “single layer” by the submitted amendment. The 112(a) rejection regarding the language “an adhesive disposed over the light emitting diode” is maintained since Applicant does not provide parts of the specification that support such claim language. It is not clear whether the Applicant is pointing to the recess 126 under the light emitting element 134, in such case, the claims do not align with the subject matter of the specification. It is recommended that the Applicant clearly claims the structure of the recess under LED 134, in addition to the surrounding structure in order to overcome the prior of record. Response to Arguments Applicant's arguments filed 11/05/2025 have been fully considered but they are not persuasive. The Applicant states that “Chen, Tokunaga and Terakado fail to disclose that the adhesive has a recess, and a width of the recess is wider than a width of the light-emitting diode. As shown in FIG. 6 (reproduced above) of Tokunaga, the adhesive layer 60 (i.e., the alleged adhesive layer) does not have any recess corresponding to organic light-emitting devices 1OR/1OG/1OB, not to mention the recess that is wider than the organic light-emitting devices 1OR/1OG/1OB. In particular, the organic light-emitting devices 1OR/1OG/1OB share the same organic light-emitting layer 54, and therefore they should not be referred to as individual light- emitting diodes. Accordingly, Tokunaga is silent about the feature regarding the recess of the adhesive defined in the amended claim 1, let alone the above-emphasized feature. Therefore, Tokunaga fails to disclose or suggest the above-emphasized feature in the amended claim 1.” However, the Applicant does not point to any part of the specification to aid in the comprehension of what constitutes an adhesive that has a recess. Further, adhesive layer 60 has multiple indentations that together form recesses wider than each individual light emitting diode. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 contains the language “an adhesive disposed over the light-emitting diode.” There is no support for at this language in the specification. Claims 2-3, and 5-10 are rejected under similar rationale for depending upon a base claim that is rejected under 112(a). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (Patent number: US 9,231,034) in view of Tokunaga et al (Publication number: US 2013/0200364). Consider Claim 1, Chen et al shows a light-emitting device (see figure 4; read as display 14), comprising: (a) A substrate (see figure 4); (Read as substrate 70). (b) A light-emitting diode disposed on the substrate (see figure 4, column 7, lines 45-67); (A current passes through organic light emitting diode emissive electroluminescent layer (emissive layer) 56). (c) A first layer disposed on the substrate and having an opening, wherein at least a portion of the light-emitting diode is disposed in the opening of the first layer (see figure 4, column 7, lines 45-67; column 8, lines 1-16); (The first layer is read as the layer between the substrate 70 and the horizontal line under the anode 60. The opening is read as the opening formed by anode 60). (d) A color filter layer disposed on the light-emitting diode (figure 4); (Read as color filter element 66). (e) A second layer disposed on the first layer and having an opening overlapped with the opening of the first layer, (see figure 4); (The second layer is read as the layer above the horizontal line under anode 60. The opening formed by anode 60 is between the first and second layers as defined herein). (f) Wherein the second layer is configured to shield a light emitted from the light-emitting diode, the opening of the second layer has a maximum width, and the minimum width of the opening of the second layer is measured closer to the substrate than the maximum width of the opening of the second layer (see figure 4, column 7, lines 45-67; column 8, lines 1-16); (Read as black matrix. Black matrix 72 may prevent stray light from exiting display 14). (g) Wherein in a cross-sectional view of the light-emitting device, a minimum width of the opening of the first layer is less than the minimum width of the opening of the second layer (see figure 4); (The opening formed by anode 60 is between the first layer and the second layer as defined herein. The width of the opening increases as the opening transitions from the first layer to the second layer). However, Chen does not specifically show an adhesive disposed over the light emitting diode, and the second layer disposed on the adhesive, wherein the adhesive has a recess, and a width of the recess is wider than a width of the light emitting diode. In related art, Tokunaga et al shows an adhesive disposed on the light emitting diode, and the second layer disposed on the adhesive, wherein the adhesive has a recess, and a width of the recess is wider than a width of the light emitting diode (see figure 6 and paragraph 96). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the position of the adhesive layer 60 below the color filter 72 into the color filter structure of Chen in order to bond the color filter and the light shielding layer to the substrate (see Tokunaga et al; paragraphs 95-97). Consider Claim 2, Chen et al shows that the color filter layer overlaps with the opening of the first layer (see figure 4); (Where the color filter 66 is above (overlapping) the opening. The Applicant does not define the manner of overlapping). Consider Claim 3, Chen et al shows that a width of the color filter layer is greater than the minimum width of the opening of the first layer (see figure 4); (The term “width” can be read as a vertical or horizontal width. It is merely a word that defines a dimension. However, if taken horizontally or vertically, both dimensions of color filter 66 are greater than the minimum width (the bottom part) of the opening of the first layer). Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (Patent number: US 9,231,034) in view of Tokunaga et al in view of Terakado et al (Publication number: US 2006/0012288). Consider Claim 5, Chen et al, in view of Tokunaga shows a first transistor (see figure 4); (read as transistor 54); however, Chen et al does not specifically show a first transistor and a second transistor disposed on the substrate, wherein the first transistor and the second transistor are electrically connected to the light-emitting diode. In the same field of endeavor, Terakado et al shows a first transistor and a second transistor disposed on the substrate, wherein the first transistor and the second transistor are electrically connected to the light-emitting diode (see figure 5; paragraphs 56 and 57); (Read as transistor TFT1 and TFT 2). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to add the switching transistor of Terakado into the transistor structure of Chen, and Tokunaga in order to select pixels by the scanning line (see Terakado et al; paragraphs 56-58). Consider Claim 6, Terakado et al show that the second transistor overlaps with the opening of the first layer (see Terakado et al; paragraphs 56-58); (Adding the switching TFT of Terakado into the TFT structure of Chen et al will place the switching TFT in an overlapping position. The Applicant does not specify the manner of overlapping). Consider Claim 7, Terakado et al show that the first transistor is electrically connected to the light-emitting diode via the second transistor; a conductive connection portion disposed on the substrate, wherein the first transistor is electrically connected to the second transistor via the conductive connection portion (see figure 5; paragraphs 56 and 57). Consider Claim 9, Terakado et al shows that the conductive connection portion and a gate electrode of the second transistor are in the same layer (see figure 5). Consider Claim 10, Terakado et al shows that the first transistor comprises a first semiconductor layer, the second transistor comprises a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer overlap with the color filter layer (see figure 5; paragraphs 56 and 57); (The thin film transistor TFT 1 has the gate electrode thereof connected to the scanning line GL and the drain electrode thereof connected to the data line DL. Further, the gate electrode of the thin film transistor TFT 2 is connected to the source electrode of the thin film transistor TFT 1). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 01/15/2026
Read full office action

Prosecution Timeline

Apr 02, 2024
Application Filed
Oct 27, 2024
Non-Final Rejection — §103, §112
Jan 25, 2025
Response Filed
Apr 21, 2025
Final Rejection — §103, §112
Jun 21, 2025
Request for Continued Examination
Jun 25, 2025
Response after Non-Final Action
Aug 08, 2025
Non-Final Rejection — §103, §112
Nov 05, 2025
Response Filed
Jan 15, 2026
Final Rejection — §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+8.0%)
3y 0m
Median Time to Grant
High
PTA Risk
Based on 991 resolved cases by this examiner. Grant probability derived from career allow rate.

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