DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Dudzik (“Ultra-stable, low-noise two-stage current source concept for electronics and laser applications”, IET Circuits, Devices & Systems, 2017).
Claim 1 recites an integrated circuit comprising a current source configured to generate a control current whose intensity is modulated by an input signal, comprising a first stage for a constant component and a second stage for a modulated component.
Claim 1 Limitation
Disclosure in Dudzik
An integrated circuit comprising a current source
Dudzik discloses a "two-stage current source" integrated circuit module.
Configured to generate a control current whose intensity is modulated by an input signal
Dudzik teaches an output current IOUT modulated by input Uin (where IS2=k⋅Uin).
First stage configured to autonomously generate a constant component
Dudzik discloses a "first current stage" (CS1) which provides most of the load current (IS1) as an "autonomous source".
Second stage configured to autonomously generate a modulated component
Dudzik discloses a "second stage" (CS2) which is a "precise current source" generating IS2 based on Uin, which is then added to IS1.
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Fig. 2 of Dudzik, Schematic representation of the two-stage current source.
Figures: Figure 1(a) (p. 614) shows the parallel connection of CS1 and CS2 forming IOUT, and Figure 2 (p. 614) provides the schematic representation of the first stage (CS1) and second stage (CS2).
Claim 7 recites a method of generating a control current modulated by an input signal, comprising a first autonomous generation of a constant component and a second autonomous generation of a modulated component.
Claim 7 Limitation
Disclosure in Dudzik
Generating a control current whose intensity is modulated by an input signal
Dudzik discloses generating IOUT=IS1+IS2 where IS2 is modulated by input voltage Uin.
First autonomous generation of a constant component
Dudzik teaches CS1 as an "autonomous source" generating constant component IS1.
Second autonomous generation of a control current component that is modulated
Dudzik teaches the second stage (CS2) performs "fast correction" to generate modulated component IS2 autonomously.
Specific Evidence from Dudzik
Two-Stage Architecture: Dudzik explicitly labels the circuit as a "two-stage current source concept".
Stage 1 (Constant Component): The paper states: "The CS1 is an autonomous source, which provides most of the load current (the first current stage).".
Stage 2 (Modulated Component): The paper states: "While the CS2 is a precise current source controlled by voltage across sense resistor (RSENSE)... Its operating current (IS2) is... added to the main IS1 current, forming an output current IOUT".
Input Modulation: Equation (1) on page 614, column 2, line 18, defines the modulation: "IS2=k⋅Uin," where Uin is the input signal that modulates the control current.
The independent claims 1 and 7 are anticipated because Dudzik discloses each element of the claims arranged as recited.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-6 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Dudzik
Claims 2, 3 (Current Mirror/Reference): Dudzik teaches a two-stage current source using an "autonomous source" (CS1) and a "precise current source" (CS2) (p. 614, Fig. 1). It is well-understood by a person of ordinary skill in the art (POSITA) that current sources at the integrated circuit level are standardly implemented using current mirror assemblies for high precision and temperature stability. Incorporating current mirrors into the stages disclosed in Dudzik to achieve the claimed stability is a matter of standard design choice.
Claim 4 (Proportional to AC Amplitude): Dudzik discloses a control loop where the modulation is based on the feedback of the output current (p. 614, Fig. 2). Adjusting the modulation sensitivity to be proportional to an AC input amplitude is a predictable modification to optimize the performance of the CS2 stage.
Claims 5 & 6 (System/Control Loop): Dudzik explicitly lists the application of his two-stage current source in "electronics and laser applications" (Title, p. 613). Using a current source to control a system via a control loop is the entire purpose of Dudzik’s architecture. Applying this to an "optical system" (Claim 6) is specifically taught by Dudzik’s focus on laser diode applications (p. 615, References).
Claim 8: Dudzik teaches the use of an LT3081 (CS1) which internally requires a reference current/voltage to function as an "autonomous source." It would be obvious to a POSITA that both stages of the current source require a common reference foundation (the reference current) to ensure the stages are "decorrelated" or "autonomous" while still being referenced to the same system ground/supply, as suggested by Dudzik's schematic in Fig. 2.
Claim 9 (Injection/Extraction): Dudzik explicitly teaches that the current IS2 is "added to the main IS1 current" (p. 614, col. 2, line 21). Injecting or extracting current from a reference node is the fundamental method of creating a modulated current source from a constant bias, which is the exact function of Dudzik’s CS2 stage.
Claim 10 (Proportional to Average Value): Dudzik’s correction circuit (CS2) responds to fluctuations detected at the sense resistor RSENSE. Operating this circuit to respond to an average value of a signal is a standard technique in control theory to stabilize DC components, which would be obvious to a POSITA seeking to further minimize noise in the Dudzik system.
Claim 11 recites controlling a system via a control loop. Dudzik's entire paper is dedicated to the "theory of operation for setup" of a control loop system used to stabilize current for high-performance applications (p. 614, Fig. 1). The integration of such a loop to control an output signal is the primary teaching of the reference.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim 7 but would be allowable if rewritten in independent form including all the limitations of the base claim 5 and any intervening claims.
Claim 12 requires generating an AC output signal of the system by a crystal oscillator, where the AC output signal of the system is the AC input signal of the control loop.
While Dudzik teaches using his two-stage current source to stabilize currents for laser applications, he does not explicitly describe the use of a crystal oscillator as the load/system. While a POSITA might argue that a current source can power any load (including an oscillator), the specific feedback loop configuration where the crystal oscillator itself provides the AC input signal to the control loop is not disclosed in the Dudzik paper. Unless this configuration is considered standard "well-known art" by the Examiner (which is unlikely for this specific feedback integration), this claim is currently distinguished from the cited prior art.
Conclusion
The prior arts, Akbar et al. (“Design, Fabrication, and Characterization of Ultralow Current Operational-Amplifier in the Weak Inversion Mode in XFAB-XT018 Technology”, 2016 IEEE), Zhao et al. (CN113315509A), Yum et al., (High-Efficiency Linear RF Amplifier—A Unified Circuit Approach to Achieving Compactness and Low Distortion, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 8, AUGUST 2006), PATEL et al. (IN201941045363 A), Woo et al., (“ULTRA-LOW-NOISE TRANSIMPEDANCE AMPLIFIER FOR HIGH-PERFORMANCE MEMS RESONANT GYROSCOPES”, 2017 IEEE Transducers 2017), Gundu, Anil Kumar, (“The Beta-Multiplier: A Step-by-Step Guide to Understanding”) and Khesbak et al. (US 2023/0063006 A1) made of record and not relied upon is considered pertinent to applicant's disclosure.
Woo et al. (IEEE) Woo et al. describe an ultra-low-noise transimpedance amplifier (TIA) for capacitive MEMS sensors that utilizes a digitally-controlled floating resistor and a beta-multiplier current generator to provide bias current. While this reference teaches a precision current source with temperature and voltage tolerance, it does not disclose a two-stage architecture where one stage autonomously generates a constant component and a separate second stage generates an input-signal-modulated component.
Akbar et al. (IEEE) Akbar et al. present a rail-to-rail CMOS operational amplifier designed for ultra-low-power operation in the weak inversion regime. The circuitry incorporates a beta-multiplier current source to provide bias currents that are stable against temperature variations. However, the paper is focused on transistor biasing and matching layout techniques rather than the specific two-stage autonomous constant/modulated current generation architecture claimed in Claim 1.
Patel et al. (Indian Patent) The Patel et al. application describes a capless Low Dropout Regulator (LDO) designed to provide a stable, programmable DC output voltage. The system includes a Band Gap Multiplier (BMR) for reference current and a feedback and trim circuit for regulation. As a voltage regulation system rather than a modulated current source, it fails to teach the autonomous generation of constant and input-signal-modulated current components required by Claim 1.
Zhao et al. (CN Patent) Zhao et al. disclose a phase-locked loop (PLL) circuit where a modulation circuit outputs first and second feedback currents based on modulation voltage and a frequency division control signal. While this reference involves currents that change based on control inputs, it is specifically configured for PLL loop stability and frequency synthesis rather than the dual-stage, autonomous constant/modulated current generation claimed in Claim 1.
Khesbak et al. (US Patent Pub) Khesbak et al. describe an adaptive envelope tracking system for power amplifiers where an error amplifier and DC-to-DC converter operate in parallel to generate a supply voltage based on the bandwidth of an RF envelope signal. This system focuses on controlling power amplifier supply voltage via envelope signal bandwidth detection rather than generating a control current with an autonomous constant stage and an autonomous signal-modulated stage as defined in Claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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