DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (e.g., Claims 1-11) in the reply filed on August 24, 2026, is acknowledged. Therefore, the restriction/election requirement dated July 7th, 2026, is hereby made FINAL.
Status of Claims
Pursuant to Applicant’s reply to restriction/election requirement filed August 24, 2026, Claims 12-20 are withdrawn as being drawn to a non-elected invention and Claims 1-11 are pending the within examination.
Claim Objections
Claim 2 is objected to because of the following informalities and/or typographical errors
a) “in coupled” should read “is coupled”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “gate lines” is an undefined threshold which renders Claim 2 indefinite. The term is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised. More specifically, the metes and bounds of the limitations as stated in Claim 2 is unclear to the Examiner, as “gate lines” is not properly defined or used in the specification; it is unclear whether “gate lines” is intended to correspond to the specification’s use of the term ‘word lines’. For the purposes of compact prosecution, the Examiner will apply broadest reasonable interpretation when the terms “gate lines” is invoked. When referring to “gate lines”, the Examiner will interpret that as “word lines” given their equivalent function.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
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Annotated Fig. 17 - Zhu
Claim(s) 1-4 and 6-11 is/are rejected under 35 U.S.C 103 as being unpatentable over Zhu et al. (US 20230060149 A1), and in further view of Lim et al. (US 20150243675 A1).
As to Claim 1, Zhu teaches: A semiconductor device (3D memory device 1700, Fig. 17), comprising:
vertical transistors (vertical transistors 1726) each comprising:
a semiconductor layer (semiconductor body 1730) extending along a vertical direction ([0121] “a semiconductor body 1730 (the active region in which a channel can form) extending vertically (in the z-direction)”); and
a gate structure (gate structure 1736) coupled with one side of the semiconductor layer (semiconductor body 1730, [0121] “gate structure 1736 in contact with one side of semiconductor body 1730”);
storage units (capacitor 1728) each coupled with the semiconductor layer (semiconductor body 1730) of the vertical transistor (Fig.17, [0120] “capacitor 1728 (e.g., an example of storage unit 212 in FIG. 2 ) coupled to the vertical transistor 1726”) ; and
a bonding layer (bonding layer 1720) configured to couple the vertical transistors (vertical transistors 1726) with a peripheral circuit (peripheral circuit 1712, Fig.17, [0117] “In practice, bonding interface 106 can be a layer with a certain thickness that includes the top surface of bonding layer 1718 of first semiconductor structure 102 and the bottom surface of bonding layer 1720 of second semiconductor structure 104.”), wherein the vertical transistors (vertical transistors 1726) are disposed between the bonding layer (bonding layer 1720) and the storage units (Fig. 17, capacitor 1728).
Zhu does not teach: having a leakage value is lower than a pico-ampere and. Zhu does teach a semiconductor layer [semiconductor body 1730] that extends vertically. Additionally, Zhu discloses that multi-gate transistors lead to a much better leakage performance compared to planar transistors but remains silent about the specific leakage value of the semiconductor layer.
However, in an analogous art Lim teaches: a semiconductor layer (vertical channel structures 200) having a leakage value is lower than a pico-ampere and ([0075] “leakage current may be limited and/or prevented from occurring between the gate electrodes 220 and the vertical channel structures 200”). A prima facie case of obviousness exists where the claimed ranges or amounts “overlap or lie inside ranges disclosed by the prior art”. See MPEP 2144.05. Lim discloses leakage current can be prevented from forming in the vertical channel structures 200, indicating a leakage value of zero amperes which lies within the given range (Lim, [0075]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Lim to modify the semiconductor layer of the 3D memory device as taught by Zhu to produce a low leakage value. One would be motivated to do so as this feature is advantageous for improved reliability in a vertical-type semiconductor device (Lim, [0075]).
As to Claim 2, Zhu/Lim teaches: The semiconductor device of claim 1 (Zhu, 3D memory device 1700, Fig. 17), wherein further comprises:
bit lines (Zhu, bit lines 1723) each extending along a first lateral direction (Zhu, Fig. 17, [0119] “bit line direction (e.g., the y-direction).”) and in coupled with the semiconductor layer (Zhu, Fig. 17, semiconductor body 1730);
gate lines (Zhu, word lines and gate electrode 1734, [0124] “As described above, since gate electrode 1734 may be part of a word line or extend in the word line direction (e.g., the x-direction in FIG. 18 ) as a word line”) each extending along a second lateral direction (Zhu, [0124] “word line direction (e.g., the x-direction”) and coupled with the gate structure (Zhu, gate structure 1736, [0063] “In other words, gate electrode 220 may be viewed as part of word line 204 that forms gate structure 216, or word line 204 may be viewed as the extension of gate electrode 220 to be coupled to peripheral circuits 202.”, ),
wherein the vertical direction, the first lateral direction, and the second lateral direction are perpendicular to each other (Zhu, [0124] “bit line 1723 and word line 1734 can extend in two perpendicular lateral directions, and semiconductor body 1730 of vertical transistor 1726 can extend in the vertical direction perpendicular to the two lateral directions in which bit line 1723 and word line 1734 extend”).
As to Claim 3, Zhu/Lim teaches: The semiconductor device of claim 1 (Zhu, 3D memory device 1700, Fig. 17), wherein the gate structures (Zhu, gate structure 1610) of two adjacent vertical transistors (Zhu, two adjacent vertical transistors of memory cells (e.g., 1602A and 1602B)) are disposed on a same side of each vertical transistor (Zhu, [0110] “Gate structures 1610 can be thus viewed as parts of a continuous structure extending in the word line direction at which the continuous structure abut vertical transistors in the same row on the same side.”). Examiner Note: Fig. 16 is a plan view of an embodiment so corresponding component numbers may vary slightly for this instant claim but the components remain analogous to the components disclosed by Zhu in Fig. 17.
As to Claim 4, Zhu/Lim teaches: The semiconductor device of claim 1 (Zhu, 3D memory device 1700, Fig. 17), wherein the gate structures (Zhu, gate structure 2010) of two adjacent vertical transistors (Zhu, vertical transistors 1626) are disposed on two opposite sides of each vertical transistor (Zhu, [0136] “As shown in FIG. 20 , the vertical transistor is a double-gate transistor in which gate structure 2010 abuts two opposite sides of semiconductor body 1608”). Examiner Note: Fig. 20 is a plan view of an embodiment so corresponding component numbers may vary slightly for this instant claim but the components remain analogous to the same components disclosed by Zhu in Fig. 17
As to Claim 6, Zhu/Lim teaches: The semiconductor device of claim 1 (Zhu, 3D memory device 1700, Fig. 17), wherein the gate structure (Zhu, gate structure 1736) comprises a gate electrode (Zhu, gate electrode 1734), and a gate dielectric (Zhu, gate dielectric 1732) between the gate electrode (Zhu, gate electrode 1734) and the semiconductor layer (Zhu, Fig.17, [0121] “gate dielectric 1732 laterally between gate electrode 1734 and semiconductor body 1730“).
As to Claim 7, Zhu/Lim teaches: The semiconductor device of claim 1 (Zhu, 3D memory device 1700, Fig. 17), wherein each vertical transistor (Zhu, vertical transistors 1726) is coupled with a corresponding storage unit (Zhu, capacitor 1728) through a direct ohmic contact or a storage node contact (Zhu, capacitor contact 1742, [0127] “In some implementations, capacitor contact 1742 is an ohmic contact”; [0127] “capacitor 1728 includes a first electrode above and coupled to source or drain 1738 of vertical transistor 1726, e.g., the upper end of semiconductor body 1730, via a capacitor contact 1742”).
As to Claim 8, Zhu/Lim teaches: The semiconductor device of claim 1 (Zhu, 3D memory device 1700, Fig. 17) , wherein further comprises a peripheral circuit (Zhu, peripheral circuit 1712, [0116] “first semiconductor structure 102 can further include a bonding layer 1718 at bonding interface 106 and above interconnect layer 1716 and peripheral circuits 1712.”) coupled to the vertical transistors (Zhu, vertical transistors 1726) across the bonding layer (Zhu, bonding layer 1720, Fig. 17, [0116] “bonding layer 1720 can be used for hybrid bonding“; [0117] “In practice, bonding interface 106 can be a layer with a certain thickness that includes the top surface of bonding layer 1718 of first semiconductor structure 102 and the bottom surface of bonding layer 1720 of second semiconductor structure 104.”).
As to Claim 9, Zhu/Lim teaches: The semiconductor device of claim 8 (Zhu, 3D memory device 1700, Fig. 17), wherein further comprises a pad-out interconnect layer (Zhu, pad-out interconnect layer 1750), and the storage units (Zhu, capacitors 1728) are disposed between the vertical transistors (Zhu, vertical transistors 1726) and the pad-out interconnect layer (Zhu, pad-out interconnect layer 1750, Fig. 17, [0133] “Capacitors 1728 are disposed vertically between vertical transistors 1726 and pad-out interconnect layer 1750”).
As to Claim 10, Zhu/Lim teaches: The semiconductor device of claim 8 (Zhu, 3D memory device 1700, Fig. 17) as discussed above in addressing claim 1. Zhu further teaches, in a separate embodiment wherein further comprises a pad-out interconnect layer (Zhu, pad-out interconnect layer 650), and the peripheral circuit (Zhu, peripheral circuit 612) is disposed between the pad-out interconnect layer (Zhu, pad-out interconnect layer 650), and the vertical transistors (Zhu, Fig. 6B, vertical transistors 626).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the device taught in the first embodiment [Fig. 17] with the device in the second embodiment [Fig.6B] such that semiconductor structure with the peripheral circuit comprised the pad-out interconnect layer and substrate. This would be done to achieve a different desired design in regard to the location of the pad-out interconnect layer.
Claim(s) 11 is/are rejected under 35 U.S.C 103 as being unpatentable over Zhu/Lim as applied to Claims 1-4 and 6-10 above, and in further view of Cho et al. (US 20220384661 A1).
As to Claim 11, Zhu/Lim teaches: The semiconductor device of claim 1 (Zhu, 3D memory device 1700, Fig. 17), wherein the
Zhu/Lim does not explicitly teach: semiconductor layer comprises one or a combination of InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, and InxGayO. Zhu does teach a semiconductor layer [semiconductor body 1730] that can be composed of silicon crystalline silicon but does not disclose the semiconductor layer comprising one or a combination of the materials from the instant claim [0062].
However, in an analogous art, Cho teaches: semiconductor layer (channel layer 130) comprises one or a combination of InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, and InxGayO ([0035] “the channel layer 130 may include an oxide semiconductor containing indium (In). The oxide semiconductor may be one of indium-gallium-zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin gallium oxide (ITGO), indium tungsten oxide (IWO), indium tin oxide (ITO)“). Note: The claims recite at least one of the materials listed, Cho teaches InxGayZnzO which satisfies this limitation.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Cho to modify the composition of the semiconductor layer as taught by Zhu/Lim. One would be motivated to do so as this compound is advantageous for stickability and contributing to a low leakage current (Cho, [0080]).
Allowable Subject Matter
Claims 5 would be allowable if rewritten to be independent. The following is an Examiner’s statement of reasons for allowance.
As to Claim 5, Zhu/Lim teaches: The semiconductor device of claim 1 (Zhu, 3D memory device 1700, Fig. 17), wherein the semiconductor layer (Zhu, semiconductor body 1730) comprises:
a vertical portion extending along the vertical direction (Zhu, [0122] “semiconductor body 1730 can have a larger vertical dimension (e.g., the depth) than that of gate electrode 1734 (e.g., in the z-direction), and neither the upper end nor the lower end of semiconductor body 1730 is flush with the respective end of gate electrode 1734.”) ; and
the vertical direction and the second lateral direction are perpendicular to each other (Zhu, [0124] “That is, bit line 1723 and word line 1734 can extend in two perpendicular lateral directions, and semiconductor body 1730 of vertical transistor 1726 can extend in the vertical direction perpendicular to the two lateral directions in which bit line 1723 and word line 1734 extend”).
Zhu/Lim fails to disclose the following limitations: an extending portion extending from an end of the vertical portion towards an adjacent vertical transistor along a second lateral direction; wherein
the extending portion is coupled with the storage unit; and. Zhu/Lim does teach a storage unit [Zhu, capacitor 1728] and a semiconductor layer [Zhu, semiconductor body 1730] extending in the vertical direction but fails to disclose the semiconductor extending towards adjacent vertical transistors wherein the extending portion is coupled to a storage unit.
Furthermore, none of the cited prior art of record, taken alone or in combination of one another, discloses or renders obvious the method as described above in full context of Claim 5 of the instant application. Therefore, Claim 5 contains allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mashal Ahmed whose telephone number is (571)270-1754. The examiner can normally be reached M-F, 9AM to 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MASHAL AHMED/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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