DETAILED ACTION
This office action is in response to the application filed on 04/02/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected group, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/26/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/02/2024 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claim 10. Therefore, the “wherein the control circuitry for each series-stacked half bridge generates phase shifted drive signals for at least the low side switch of each series-stacked half bridge by comparing the reference current signal to a plurality of phase shifted carrier signals” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 5 and 15 are objected to because of the following informalities: Claims 1 and 11 recites “coupled to a low side node”, “to a respective high side node” and “of a corresponding series” it appears this should be change to “coupled to the low side node”, “to the respective high side node” and “of the corresponding series”. Claim 5 recites “a corresponding DC-DC converter” this should be change to “the corresponding DC-DC converter”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamada US 2015/0372614.
Regarding Claim 1, Yamada teaches (Figures 2-4) An AC/DC power supply (Fig. 2) comprising: a rectifier (DB) that receives an AC input voltage (1) and produces a rectified output voltage (Vr1); a plurality of series-stacked half bridges (11), each of the plurality of series-stacked half bridges comprises an upper switching device (8) and a lower switching device (7), the plurality of series-stacked half bridges including: a first series-stacked half bridge having a switch node (node between switches) coupled to the rectifier by a single inductor (6) and operable to produce a first floating DC bus across high side and low side nodes (Ea); and one or more additional series-stacked half bridges each having a switch node coupled to a low side node of a preceding series-stacked half bridge (Fig. 2, at Na) and operable to produce a floating DC bus across high side and low side nodes (Eb); and a plurality of isolated DC-DC converters (30) each having an input coupled to a respective high side node and low side node of a corresponding series-stacked half bridge (see Fig. 2) and all having their outputs connected in parallel to provide a DC output voltage for the AC/DC power supply (see fig. 2). (For Example: Par. 81-92)
Regarding Claim 2, teaches (Figures 2-4) wherein the upper switching device is a diode (8), and the lower switching device is a transistor(7).
Regarding Claim 3, teaches (Figures 2-4) further comprising a plurality of bulk capacitors (9) coupled across the high side and low side nodes of respective series-stacked half bridges (at 11).
Regarding Claim 4, teaches (Figures 2-4) further comprising control circuitry (Fig. 3 and controller for 30) for the plurality of isolated DC-DC converters (30) that ensures equal power sharing between the plurality of isolated DC-DC converters (par. 87). (For Example: Par. 81-92)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Zhang US 2021/0408927.
Regarding Claim 5, Yamada teaches the system.
Yamada does not teach the control circuitry that ensures equal power sharing between the plurality of isolated DC-DC converters compares a target floating DC bus voltage to a voltage of each floating DC bus and generates therefrom a small variation of a manipulated variable of a controller of a corresponding DC-DC converter.
Zhang teaches (Figures 10b-c) wherein the control circuitry (control) that ensures equal power sharing (par. 32 and 136) between the plurality of isolated DC-DC converters (at 500) compares a target floating DC bus voltage (Vr) to a voltage of each floating DC bus (with voltage balancing loop, fig. 10b) and generates therefrom a small variation of a manipulated variable of a controller (delta Vn) of a corresponding DC-DC converter . (For Example: Par. 144-153)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamada to include wherein the control circuitry that ensures equal power sharing between the plurality of isolated DC-DC converters compares a target floating DC bus voltage to a voltage of each floating DC bus and generates therefrom a small variation of a manipulated variable of a controller of a corresponding DC-DC converter, as taught by Zhang to minimize switching losses and allow high-frequency operation.
Regarding Claim 6-7, teaches (Figures 2-4) the system.
Yamada does not teach wherein the manipulated variable is switching frequency of the corresponding DC-DC converter; wherein the manipulated variable is a resonant capacitor voltage of the corresponding DC-DC converter.
Zhang teaches (Figures 5 and 10b-c) wherein the manipulated variable is switching frequency of the corresponding DC-DC converter (par. 122); wherein the manipulated variable is a resonant capacitor voltage of the corresponding DC-DC converter (par. 114, see fig. 5). (For example: Par. 112-118 and 126)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamada to include wherein the manipulated variable is switching frequency of the corresponding DC-DC converter; wherein the manipulated variable is a resonant capacitor voltage of the corresponding DC-DC converter, as taught by Zhang to minimize switching losses and allow high-frequency operation.
Regarding Claim 13, teaches (Figures 2-4) the system.
Yamada does not teach wherein the isolated DC-DC converters are LLC converters.
Zhang teaches (Figures 5 and 10b-c) wherein the isolated DC-DC converters are LLC converters (500). (For example: Par. 112-118 and 126)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamada to include wherein the isolated DC-DC converters are LLC converters, as taught by Zhang to minimize switching losses and allow high-frequency operation.
Regarding Claim 15, Yamada teaches (Figures 2-4) a unidirectional AC/DC power supply (Fig. 2) comprising: a rectifier (DB) that receives an AC input voltage (at 1) and produces a rectified output voltage (Vr1); a plurality of series-stacked half bridges (11), wherein each of the plurality of series-stacked half bridges further comprises an upper switching device and a lower switching device (7-8), the plurality of series-stacked half bridges including: a first series-stacked half bridge (11a) having a switch node coupled to the rectifier by a single inductor (6) and operable to produce a first floating DC bus (Ea) across high side and low side nodes; and one or more additional series-stacked half bridges (11b-c) each having a switch node coupled to a low side node of a preceding series-stacked half bridge (See fig. 2) and operable to produce a floating DC bus across high side and low side nodes (Eb and Ec); a plurality of bulk capacitors (9) coupled across the high side and low side nodes of respective series-stacked half bridges; and a plurality of converters (30) each having an input coupled to a respective high side node and low side node of a corresponding series-stacked half bridge (see fig. 2) and all having their outputs connected in parallel to provide a DC output voltage for the AC/DC power supply (see fig. 2). (For Example: Par. 81-92)
Yamada does not teach wherein the isolated DC-DC converters are LLC converters.
Zhang teaches (Figures 5 and 10b-c) wherein the isolated DC-DC converters are LLC converters (500). (For example: Par. 112-118 and 126)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamada to include wherein the isolated DC-DC converters are LLC converters, as taught by Zhang to minimize switching losses and allow high-frequency operation.
Regarding Claim 16, Yamada teaches the system.
Yamada does not teach t comprising control circuitry for the plurality of LLC converters that ensures equal power sharing between the plurality of LLC converters.
Zhang teaches (Figures 10b-c) comprising control circuitry(control) for the plurality of LLC converters (at 500) that ensures equal power sharing between the plurality of LLC converters(par. 136). (For Example: Par. 32 and 144-153)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamada to include wherein the control circuitry that ensures equal power sharing between the plurality of isolated DC-DC converters compares a target floating DC bus voltage to a voltage of each floating DC bus and generates therefrom a small variation of a manipulated variable of a controller of a corresponding DC-DC converter, as taught by Zhang to minimize switching losses and allow high-frequency operation.
Claim(s) 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Deboy US 2016/0072398.
Regarding Claim 8, Yamada teaches (Figures 2-4) further comprising control circuitry (at fig. 3) for the plurality of series-stacked half bridges (11) that compares the rectified output voltage (E) and generates therefrom a reference current signal (command IL) for a current controller of each series-stacked half bridge (generating individual 7a-c signals). (For Example: Par. 81-92)
Yamada does not teach that compares the rectified output voltage (E) to a sum of voltages on the isolated DC busses and generates therefrom a reference current signal for a current controller.
Deboy teaches (Figures 35-36) that compares the rectified output voltage (V2) to a sum of voltages on the isolated DC busses (Vout) and generates therefrom a reference current signal (Iout ref) for a current controller (52). (For Example: Par. 220-224)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamada to include that compares the rectified output voltage (E) to a sum of voltages on the isolated DC busses and generates therefrom a reference current signal for a current controller, as taught by Deboy to keep losses that may occur in connection with the power conversion as low as possible.
Regarding Claim 9, Yamada teaches (Figures 2-4) wherein the current controller is selected from the group consisting of a peak current controller (peak) and an average current controller. (For Example: Par. 12 and 25)
Yamada does not teach and operates in a mode selected from a continuous conduction mode, a discontinuous conduction mode, and a critical conduction mode.
Deboy teaches operates in a mode selected from a continuous conduction mode (par. 377), a discontinuous conduction mode, and a critical conduction mode. (See Abstract)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamada to include operates in a mode selected from a continuous conduction mode, a discontinuous conduction mode, and a critical conduction mode, as taught by Deboy to keep losses that may occur in connection with the power conversion as low as possible.
Regarding Claim 10, Yamada teaches (Figures 2-4) wherein the control circuitry (at fig. 3) for each series-stacked half bridge generates phase shifted drive signals for at least the low side switch of each series-stacked half bridge (see fig. 4) by comparing the reference current signal to a plurality of phase shifted carrier signals (see fig. 4, carrier a-c), wherein the carrier signals are phase shifted with respect to each other by 360/n degrees, where n is a number of series-stacked half bridges in the plurality (N=3, phase shift 120 degrees, par. 91). (For Example: Par. 88-92, 127-130)
Regarding Claims 11-12, Yamada teaches (Figures 2-4) wherein n is 2; where n is 3. (For Example: Par. 76)
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Tomioka US 2025/0070679.
Regarding Claim 14, Yamada teaches (Figures 2-4) the system.
Yamada does not teach wherein the isolated DC-DC converters are CLLC converters.
Tomioka teaches (Figure 9a) wherein the isolated DC-DC converters are LLC converters (Fig. 9a).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamada to include w wherein the isolated DC-DC converters are LLC converters, as taught by Tomioka to provide a power conversion device capable of achieving high efficiency even if an input voltage of a boost converter can have two or more types of input voltage levels.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Zhang and further in view of Deboy US 2016/0072398.
Regarding Claim 17, Yamada teaches (Figures 2-4) further comprising control circuitry (at fig. 3) for the plurality of series-stacked half bridges (11) that compares the rectified output voltage (E) and generates therefrom a reference current signal (command IL) for a current controller of each series-stacked half bridge (generating individual 7a-c signals). (For Example: Par. 81-92)
Yamada does not teach that compares the rectified output voltage (E) to a sum of voltages on the isolated DC busses and generates therefrom a reference current signal for a current controller.
Deboy teaches (Figures 35-36) that compares the rectified output voltage (V2) to a sum of voltages on the isolated DC busses (Vout) and generates therefrom a reference current signal (Iout ref) for a current controller (52). (For Example: Par. 220-224)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamada to include that compares the rectified output voltage (E) to a sum of voltages on the isolated DC busses and generates therefrom a reference current signal for a current controller, as taught by Deboy to keep losses that may occur in connection with the power conversion as low as possible.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838