Final Rejection
Reissue Applications
For reissue applications filed on or after September 16, 2012, all references to 35
U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Claim Status
Amended patent claims 1 and 6-9 and new claims 22-26, 32, 33, and 37 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 6, 9, 23, 25, and 37 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is directed to the embodiment shown in Figure 11 and disclosed throughout the specification but particularly in col.17, line 51 to col.18, line 10. Figure 11 is directed to stacked structure array units which together form a single micro semiconductor stacked structure, not to a “plurality of micro semiconductor stacked structures arranged in an array” as is currently claimed. These particular structures are shown in Figures 3A, 4B, 5, and 6 instead.
Thus, the claim terminology used in claim 1 is vague and confusing, rendering the claim indefinite. An additional example, in line 6 wherein it is recited that “the micro semiconductor stacked structures arranged in the array.” However, as explained above, there is only a single micro semiconductor structure 10g in Figure 11 and it is not arranged in an array. Instead, the array units are stacked to form a micro semiconductor stacked structure. In lines 7-8, the phrase “mapped to a first connection to a first micro semiconductor stacked structure” is confusing grammatically and with respect to Figure 11. Instead, it should read “mapped to a first connection of a first stacked structure array unit.” Similarly, in lines 8-10 the phrase “a second input of the external electronic control structure is mapped to a second connection to a second connection to a second micro semiconductor stacked structure of the plurality of micro semiconductor stacked structures” renders the claim vague and indefinite as confusing grammatically and with respect to Figure 11. Instead, the phrase should read “a second input of the external electronic control structure is mapped to a second connection of a second stacked structure array unit of the plurality of stacked structure array units.” There are several more instances of incorrect usage of the term “micro semiconductor stacked structures” throughout claims 1, 6, 9, 23, 25, and 37. Patent Owner is urged to amend claim 1 to correspond correctly with the apparatus terminology used to describe Figure 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-8, 23, 25, and 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0073248 to Haerle et al. (hereinafter Haerle) in view of US 2018/0374828 to Liao et al. (hereinafter Liao) and US 2012/0182284 to Shieh et al. (hereinafter Shieh).
With respect to claims 1, 7, 8, 23, Haerle teaches a plurality of stacked array units 20R,G,B forming a stacked structure 20. Each array unit comprises a substrate 26R,G,B, a conductive pattern layer 24R,G,B disposed on the substrate, and one or more OLEDs
PNG
media_image1.png
340
670
media_image1.png
Greyscale
22R,G,B disposed on the substrate in an array and electrically connected to the conductive pattern layer. Further, each of the array units defines a target region where at least one of the OLEDs 22R,G,B is disposed and wherein the target regions are aligned along first and second directions perpendicular to teach other. See Fig.2. Haerle further discloses the conductive pattern (TFT) is part of an active circuit (para [0001]). Haerle is silent as to using a micro semiconductor device in place of the OLEDs and to an external electronic control structure mapped to connections on each array for control thereof.
Liao discloses a micro LED (semiconductor) display and teaches that as compared to an OLED, a micro LED “is more power efficient and has better contrast performance and visibility.” Liao further discloses a micro LED display “has better reliability and longer service life than the OLED display” See para [0003]. One of ordinary skill in the art would have found it obvious to fabricate the display of Haerle with the micro semiconductor LEDs of Liao in place of OLEDs, making the necessary changes in scale when doing so, in order to optimize factors such as brightness, efficiency, and length of use.
Shieh teaches an active matrix for display devices that are not limited to OLED displays (para 0020). Shieh discloses each pixel 20 includes a red 22, a green 23, and a blue 24 light generating element/subpixel or component and the elements may be arranged as a “stack of elements.” See para [0021]. Scan lines (inputs) 25,26,27 are mapped to a connection on each element such that each element can be activated separately from the others. A driver circuit/controller 21 is separate from the stacked elements and is located on the backplane of the active matrix (para [0022]). Shieh further teaches that a “single data driver can be used to drive all three pixel elements,” thereby reducing the number of data drivers needed and thus, the expense of fabrication. See paras [0010,0027]. Importantly, For this reason, it would have been obvious to incorporate the control structure of Shieh into the combination of Haerle with Liao. One of ordinary skill in the art would have been capable of applying this known method of enhancement to the stacked array structure of the combination and the results would have been predictable to one of ordinary skill in the art. See MPEP 2143 C.
As to claim 6, Haerle teaches a transparent glass substrate. See para [0015].
With respect to claims 25 and 26, Haerle discloses first, second, and third OLED arrays in a single pixel. Although Haerle teaches each OLED array is a different color, it would have been obvious to use two OLED arrays of the same color where it is necessary to increase brightness of one color. It has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); St. Regis Paper Co. v. Bemis Co., Inc., 193 USPQ 8,11 (7th Cir. 1977). Further, Haerle teaches that each conductive pattern layer (TFT) can control a single element or multiple elements. See para [0019].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haerle, Liao, and Shieh as applied to claim 1 above, and further in view of US 2009/0001391 to Ogihara et al. (hereinafter Ogihara).
The combination of Haerle with Liao and Shieh is silent as to bonding the stacked array units.
Ogihara discloses stacked array units 101,102,103 comprising arrays of light emitting elements 112,114,116 mounted on substrates 110a,110a,110c. Ogihara teaches that “spacers, fillers, adhesive materials or the like” may be used
PNG
media_image2.png
414
680
media_image2.png
Greyscale
PNG
media_image3.png
424
614
media_image3.png
Greyscale
between the arrays “to maintain respective gaps therebetween.” See para [0055]. It would have been obvious to a POSITA to bond the stacked array units of Haerle as modified by Liao and Shieh for the same purpose.
Claim(s) 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haerle, Liao, and Shieh as applied to claim 1 above, and further in view of US 2018/0211943 to Song et al. (hereinafter Song).
PNG
media_image4.png
342
562
media_image4.png
Greyscale
The array units of Haerle are stacked, one above the other. Although Shieh doesn’t specifically teach the relative length of the first and second inputs (scan lines), it would have been obvious that the length of the uppermost scan line would be longer than those below it where the arrays form a stair structure, as disclosed by Song. One would have found it obvious to sequentially decrease the substrate sizes of Haerle, in order to facilitate interconnection between stacks, as taught by Song.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haerle, Liao, and Shieh as applied to claim 1 above, and further in view of US 2018/0191978 to Cok et al. (hereinafter Cok).
Haerle discloses a rigid transparent substrate but is silent as to the thickness of the substrate. See paras [0015-0017]. Cok teaches displays comprising micro LEDs 60 disposed on substrate 12, wherein the substrate is a rigid or flexible transparent material such as glass, plastic, or resin. The thickness of the substrate includes thicknesses from 10 to 500 microns. See para [0107]. It would have been obvious to choose a substrate thickness within the range disclosed by Cok as suitable for the micro-LEDs of Haerle as modified by Liao and Shieh, particularly where that range has not been disclosed as critical to the invention. Further, the POSITA would have found it obvious to choose known and suitable substrates for micro LEDs, as disclosed by Cok. Only the expected results would have been achieved.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haerle, Liao, and Shieh as applied to claim 23 above, and further in view of US 2018/0197934 to Chen et al. (hereinafter Chen).
The combination of Haerle with Liao and Shieh is silent as to whether a flip-chip or vertical chip would be produced by the combination. However, Chen teaches that micro-LEDs may be either flip-chips or vertical chips. See para [0023]. Thus, it would have been obvious to choose either depending on whether the practitioner desired a conventional multidirectional LED or a unidirectional LED for use in high-luminance lighting.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haerle, Liao, and Shieh as applied to claim 1 above, and further in view of US 2018/0357460 to Smith et al. (hereinafter Smith).
The combination of Haerle with Liao and Shieh is silent to the inclusion of photo sensor chips in the structure. However, Smith discloses an optical sensor comprising a matrix of display pixels (micro LEDs) 320 and photosensor pixels 330. See Fig.3; para [0010]. The display pixel illuminates the input object and detector pixels detect reflected light from a portion of the input object. It would have been obvious to a POSITA to combine the micro LED stacked structure of Haerle modified by Liao and Shieh, with photosensor pixels in order to provide an additional usefulness to the invention of the combination. The addition of photosensor pixels would have yielded only predictable results. One skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395; B/E Aerospace, Inc. v. C&D Zodiac, Inc., 962 F.3d 1373, 1379, 2020 USPQ2d 10706 (Fed. Cir. 2020). MPEP 2143 I.A.
Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haerle, Liao, and Shieh as applied to claim 1 above, and further in view of CN 107946415 to Chi et al. (hereinafter Chi).
Haerle with Liao and Shieh fails to teach the structure is included in a VR or AR display apparatus. Chi discloses the necessary use of micro LEDs within VR/AR displays due to the need for high resolution (exceeding 1000ppi). See Background Technology. One would have found it obvious to use the micro LED structure of Haerle as modified by Liao and Shieh within a VR or AR display apparatus as one would have an expectation that the display would provide a high resolution.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are not deemed persuasive.
Patent Owner asserts that claim 1 has been amended to correspond with features shown in Figure 11. However, it appears that elements from different figures have been conflated rendering the amendments to claim 11 indefinite. Further, the new combination of references teaches the new claim limitations added to claims 1 and 37. Specifically, the external controller individually controlling each separate array is disclosed by Shieh.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 11,296,061 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to ELIZABETH MCKANE whose telephone number is
(571) 272-1275. The examiner can normally be reached on Mon-Thurs; 6:30 am -
4:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor Patricia Engle can be reached on 571-272-6660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of any application may be obtained from the
Patent Center at https://patentcenter.uspto.gov.
Should you have questions, contact the Electronic Business Center (EBC) at
866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service
Representative or access to the automated information system, call 800-786-9199 (IN
USA OR CANADA) or 571-272-1000.
/ELIZABETH L MCKANE/Specialist, Art Unit 3991
Conferees:
/LEONARDO ANDUJAR/ Primary Examiner, Art Unit 3991
/Patricia L Engle/ SPRS, Art Unit 3991