Reissue Applications
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 22 April 2026 has been entered.
Claim Status
Amended patent claims 1 and 6-9, and new claims 22-26, 32, 33, and 37-40 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 39 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In line 4 of the claim, the phrase “wherein the second end of the conductive pattern layer extends does not extend” renders the claim vague and indefinite as it cannot be determined if the conductive pattern extends to a second edge of the substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-9, 23-26, and 37-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0357315 to Oraw (hereinafter Oraw) in view of US 2012/0182284 to Shieh et al. (hereinafter Shieh) and US 2005/0073248 to Haerle et al. (hereinafter Haerle).
With respect to claims 1, 7-9, 23, 37, and 40, Oraw teaches an electronic apparatus (display), comprising a micro semiconductor (para [0041]) stacked structure 84 including a plurality of stacked structure array units (see annotated Figure 9); and an external electronic control structure 110 separated from the micro semiconductor stacked structure. Oraw discloses that conductor strips 88,94,102 “may form orthogonal X conductor strips to
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“horizontally” address any pixel color in any pixel. See para [0085]. Additionally, Oraw teaches “completely independent control over the driving of the first layer of LEDs and the second layer of LEDs” (para [0025]), suggesting a one-to-one correspondence between conductor strips 88,94,102 and the plurality of stacked structure array units. Further, as shown in the Figure above, the conductive pattern extends between adjacent micro LEDs.
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Oraw discloses a single substrate 10 supporting micro semiconductor stacked structure 84 but not a substrate for each of the stacked structure array units. However, Haerle teaches a plurality of stacked structure array units 20R,G,B forming a stacked structure 20 wherein each array unit comprises a substrate 26R,G,B. See Figure 2.
As Haerle describes embodiments using a substrate for each layer and those using a single substrate for multiple layers (Figure 3), it would have been obvious to a POSITA to use a substrate for each layer of LEDs in Oraw as one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395. The result of using a separate substrate for each layer in the manner of Haerle would be merely a less flexible display panel having more mechanical stability.
Oraw further teaches that each array unit includes a conductive pattern layer 80,90,98, and one or more micro semiconductor devices 82,92,100 electrically connected to the conductive pattern layer, the conductive pattern layer continuously extends on the substrate such that all of the micro semiconductor devices of a corresponding stacked structure array unit are electrically connected to the conductive pattern layer (see Figure 7, illustrating the conductive pattern layer 12,20,32 extending continuously), and first and second ends of the conductive pattern layer extend beyond edges of outermost micro semiconductor devices of the corresponding stacked structure array unit (see Figure 7, illustrating the conductive pattern layer extends beyond the edges of the outermost micro semiconductor devices). See also paras [0080-0081].
In the device of Oraw, each of the stacked structure array units defines a target region, and at least one of the micro semiconductor devices is disposed in the target region (Figures 7 and 9). Oraw does not teach aligning the target regions along first and second directions perpendicular to each other. However, this is known in the art as taught by Haerle and shown in Figure 2. It would have been obvious to a POSITA to align the target regions in the manner of Haerle in applications where it is desired to create more even distribution of light over the target area.
As set forth above, Oraw teaches “independent drive control of each color in each pixel” using an addressing circuit 110. See para [0091]. Such independent control would necessarily require ICs embedded in or connected to each LED in order to achieve a unique address for each LED. Haerle teaches a TFT embedded with each LED in a display device for control thereof. See para [0001]. It would have been obvious to a person of ordinary skill in the art to embed a TFT with each LED of Oraw in order to achieve the required addressing of the addressing circuit.
Oraw substantially teaches the external electronic control structure is mapped to unique connections on each array, as discussed in paras [0079, 0085, 0086, 0091]. In case it is argued that Oraw does not teach this control structure, Shieh is relied upon. Shieh teaches an active matrix for display devices that are not limited to OLED displays (para 0020). Shieh discloses each pixel 20 includes a red 22, a green 23, and a blue 24 light generating element/subpixel or component and the elements may be arranged as a “stack of elements.” See para [0021]. Scan lines (inputs) 25,26,27 are mapped to a connection on each element such that each element can be activated separately from the others. A driver circuit/controller 21 is separate from the stacked elements and is located on the backplane of the active matrix (para [0022]). Shieh further teaches that a “single data driver can be used to drive all three pixel elements,” thereby reducing the number of data drivers needed and thus, the expense of fabrication. See paras [0010,0027]. Thus, it would have been obvious to incorporate the control structure of Shieh into the display of Oraw. One of ordinary skill in the art would have been capable of applying this known method of enhancement to the stacked array structure of the combination and the results would have been predictable to one of ordinary skill in the art. See MPEP 2143 C.
As to claim 6, Oraw teaches a transparent substrate. See para [0097].
With respect to claim 24, Oraw teaches a vertical micro-LED (para [0079]).
With respect to claims 25 and 26, Oraw discloses first, second, and third micro-LED arrays in a single pixel. Although Oraw teaches each OLED array is a different color, it would have been obvious to use two OLED arrays of the same color where it is necessary to increase brightness of one color. It has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); St. Regis Paper Co. v. Bemis Co., Inc., 193 USPQ 8,11 (7th Cir. 1977). Further, Haerle teaches that each conductive pattern layer (TFT) can control a single element or multiple elements. See para [0019].
As to claim 38, Oraw discloses the second stacked structure array unit is disposed above the first array unit and the control unit is disposed adjacent the first array unit (Figures 9).
With respect to claim 39, as shown in Figure 7, the conductive pattern 12 extends to each edge of the substrate 10.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oraw, Haerle, and Shieh as applied to claim 1 above, and further in view of US 2018/0191978 to Cok et al. (hereinafter Cok).
Oraw discloses placing the micro-LEDs on a transparent substrate but is silent as to the thickness of the substrate. See para [0097]. Cok teaches displays comprising micro LEDs 60 disposed on substrate 12, wherein the substrate is a rigid or flexible transparent material such as glass, plastic, or resin. The thickness of the substrate includes thicknesses from 10 to 500 microns. See para [0107]. It would have been obvious to choose a substrate thickness within the range disclosed by Cok as suitable for the micro-LEDs of Oraw as modified by Liao and Shieh, particularly where that range has not been disclosed as critical to the invention. Further, the POSITA would have found it obvious to choose known and suitable substrates for micro LEDs, as disclosed by Cok. Only the expected results would have been achieved.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oraw, Haerle, and Shieh as applied to claim 1 above, and further in view of US 2018/0357460 to Smith et al. (hereinafter Smith).
The combination of Oraw with Haerle and Shieh is silent to the inclusion of photo sensor chips in the structure. However, Smith discloses an optical sensor comprising a matrix of display pixels (micro LEDs) 320 and photosensor pixels 330. See Fig.3; para [0010]. The display pixel illuminates the input object and detector pixels detect reflected light from a portion of the input object. It would have been obvious to a POSITA to combine the micro LED stacked structure of Oraw modified by Haerle and Shieh, with photosensor pixels in order to provide an additional usefulness to the invention of the combination. The addition of photosensor pixels would have yielded only predictable results. One skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395; B/E Aerospace, Inc. v. C&D Zodiac, Inc., 962 F.3d 1373, 1379, 2020 USPQ2d 10706 (Fed. Cir. 2020). MPEP 2143 I.A.
Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oraw, Haerle, and Shieh as applied to claim 1 above, and further in view of CN 107946415 to Chi et al. (hereinafter Chi).
Oraw with Haerle and Shieh fails to teach the structure is included in a VR or AR display apparatus. Chi discloses the necessary use of micro LEDs within VR/AR displays due to the need for high resolution (exceeding 1000ppi). See Background Technology. One would have found it obvious to use the micro LED structure of Oraw as modified by Haerle and Shieh within a VR or AR display apparatus as one would have an expectation that the display would provide a high resolution.
Claim Objections
Claim 38 is objected to because of the following informalities: In line 2 there are two instances of “is disposed.” One must be deleted. Appropriate correction is required.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 11,296,061 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to ELIZABETH MCKANE whose telephone number is
(571) 272-1275. The examiner can normally be reached on Mon-Thurs; 6:30 am -
4:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor Patricia Engle can be reached on 571-272-6660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIZABETH L MCKANE/Specialist, Art Unit 3991
Conferees: /LEONARDO ANDUJAR/ /Patricia L Engle/ Primary Examiner, Art Unit 3991 SPRS, Art Unit 3993
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