DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
Examiner states for the record that no Information Disclosure Statement is presently filed in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 1, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 8, 10, 15, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baskakov et al. (Pub. No. US 2015/0309736) in view of Shultz et al. (Pub. No. US 2009/0006801).
Claim 1:
Baskakov et al. disclose an apparatus, comprising:
a non-volatile memory [figs. 1-2; pars. 0019-0021, 0049 – backend storage 112]; and
one or more controllers coupled with the non-volatile memory and configured to cause the apparatus to [figs. 1-2; pars. 0029-0031 – swap file manager 150]:
determine that a set of write commands share a group identifier associated with a writeback procedure or target a swap area of the non-volatile memory associated with a swap procedure [pars. 0028-0036 – Writes targeting a swap file are analyzed. (“In one example, swap file manager 150 may analyze the write I/O requests as a hint to determine which block or blocks in host swap file 234 might be accessed in a single read request.”)];
determine that the writeback procedure or the swap procedure has been initiated based at least in part on determining that the set of write commands share the group identifier associated with the writeback procedure or target the swap area of the non-volatile memory associated with the swap procedure [pars. 0028-0036 – Writes targeting a swap file are analyzed. It is determined that a swap operation is being performed. (“In one example, swap file manager 150 may analyze the write I/O requests as a hint to determine which block or blocks in host swap file 234 might be accessed in a single read request.”)]; and
write, based at least in part on determining that the writeback procedure or the swap procedure has been initiated, data associated with the set of write commands to the non-volatile memory using a first type of write operation that has lower latency than a second type of write operation [pars. 0028-0036 – Writes are stored contiguously in order to reduce future read latency associated with the write. (“For example, virtualization software 104 can determine that content to be paged out of PPN 201 in a write request issued by VM 106(1) includes references to content stored on host swap file 234. In response to the determination, virtualization software 104 can request swap file manager 150 to perform the technique so that referenced block or blocks appear contiguous in host swap file 234. This can reduce future read I/O latency by minimizing the number of read I/Os that are needed to retrieve the content from host swap file 234.”)].
However, Baskakov et al. do not specifically disclose,
wherein determining that the writeback procedure or the swap procedure has been initiated is further based at least in part on a capacity of a volatile memory being insufficient for new data.
In the same field of endeavor, Shultz et al. disclose,
wherein determining that the writeback procedure or the swap procedure has been initiated is further based at least in part on a capacity of a volatile memory being insufficient for new data [par. 0021-0022 – “For example, hypervisor 40 allocates to each virtual machine 33, 34 and 35 a time share of the real processor(s) 23 and a range of virtual private memory mapped to real RAM 24.” … “Most guest operating systems include some algorithm for determining which pages of data will remain in the cache memory when the cache is full and which pages of data should remain in the working memory when the working memory is full. For example, most guest operating systems use a least recently used algorithm to outpage the least recently used data from the cache memory to external storage or swap memory when there is insufficient room in the cache memory for new data needed by the virtual machine, and use a similar algorithm to outpage the least recently used data from the working memory to external storage or swap memory when there is insufficient room in the working memory for new data needed by the virtual machine. Each swap memory is used to receive and store data paged out from cache memory and working memory as an alternative to paging out data to disk storage. Data resident in swap memory is also paged in as needed. Each guest operating system chooses whether to page out data to swap memory or to disk storage based on user-configuration of the virtual machine.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Baskakov et al. to include an eviction algorithm, as taught by Shultz et al., in order to improve performance by freeing space in the volatile memory for operation.
Claim 3 (as applied to claim 1 above):
Baskakov et al. disclose,
wherein a swap procedure comprises a procedure in which data from the volatile memory of a host system is temporarily written to the swap area of the non-volatile memory to free up space in the volatile memory [fig. 2; pars. 0019-0021 – “Backend storage 112 includes guest swap file 214 and guest swap file 224 which are configured to store guest content for VM 106(1) and 106(2), respectively. Guest content can be paged out to a guest swap file to free up resources in the corresponding VM. Backend storage 112 also includes host swap file 234 which is configured to store guest content paged out by the host OS. For example when host memory 230 is low, virtualization software 104 can page out MPN 203 or MPN 204 to host swap file 234. Backend storage 112 further includes block mapping info 212 that corresponds to guest swap file 214 and block mapping info 222 that corresponds with guest swap file 224.”].
Claim 8:
Claim 8, directed to a method, is rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis.
Claim 10 (as applied to claim 8 above):
Claim 10, directed to a method, is rejected for the same reasons set forth in the rejection of claim 3 above, mutatis mutandis.
Claim 15:
Claim 15, directed to a non-transitory computer-readable medium, is rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis.
Claim 17 (as applied to claim 15 above):
Claim 17, directed to a non-transitory computer-readable medium, is rejected for the same reasons set forth in the rejection of claim 3 above, mutatis mutandis.
Claim(s) 2, 9, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baskakov et al. (Pub. No. US 2015/0309736) in view of Shultz et al. (Pub. No. US 2009/0006801) as applied to claims 1, 8, and 15 above respectively, and further in view of Sherlock et al. (Pub. No. US 2019/0012222).
Claim 2 (as applied to claim 1 above):
Baskakov et al. and Shultz et al. disclose all the limitations above but do not specifically disclose,
wherein a writeback procedure comprises a procedure in which data from a cache of a host system is received and written to the non-volatile memory.
In the same field of endeavor, Sherlock et al. disclose,
wherein a writeback procedure comprises a procedure in which data from a cache of a host system is received and written to the non-volatile memory [par. 0042 – “Writing modified data of the cache memory 202 back to persistent memory can be performed as part of a writeback operation, which is initiated by the processor 102 whenever the processor 102 wishes to persistent modified data in the cache memory 202. In other examples, modified data can be flushed from the cache memory 202 to provide additional space in the cache memory 202 to store additional data. This latter process is part of an eviction process, where data in the cache memory 202 is evicted to make space for other data.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Baskakov et al. and Shultz et al. to include writeback cache operations, as taught by Sherlock et al., in order to improve performance by allowing the cache to be available for future operations.
Claim 9 (as applied to claim 8 above):
Claim 9, directed to a method, is rejected for the same reasons set forth in the rejection of claim 2 above, mutatis mutandis.
Claim 16 (as applied to claim 15 above):
Claim 16, directed to a non-transitory computer-readable medium, is rejected for the same reasons set forth in the rejection of claim 2 above, mutatis mutandis.
Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baskakov et al. (Pub. No. US 2015/0309736) in view of Shultz et al. (Pub. No. US 2009/0006801) as applied to claim 1, 8, and 15 above, respectively, and further in view of Schlansker et al. (Pub. No. US 2007/0174505).
Claim 4 (as applied to claim 1 above):
Baskakov et al. and Shultz et al. disclose all the limitations above but do not specifically disclose, wherein the one or more controllers are further configured to cause the apparatus to:
pause an operation based at least in part on determining that the writeback procedure or the swap procedure has been initiated; and
resume the operation based at least in part on determining that the writeback procedure or the swap procedure has ended.
In the same field of endeavor, Schlansker et al. disclose the apparatus to:
pause an operation based at least in part on determining that the writeback procedure or the swap procedure has been initiated [par. 0002 – “An operating system can unilaterally perform page swaps of so-called unpinned virtual pages. Thus, application software operating on such network systems typically accesses main memory using address translation hardware that ensures that the correct physical page is accessed, e.g., that the operating system has not initiated a page swap for the page that the software needs to access. Software access pauses during time intervals when needed data is swapped out and resumes by accessing a new physical location when data is swapped in at that location.”]; and
resume the operation based at least in part on determining that the writeback procedure or the swap procedure has ended [par. 0002 – “An operating system can unilaterally perform page swaps of so-called unpinned virtual pages. Thus, application software operating on such network systems typically accesses main memory using address translation hardware that ensures that the correct physical page is accessed, e.g., that the operating system has not initiated a page swap for the page that the software needs to access. Software access pauses during time intervals when needed data is swapped out and resumes by accessing a new physical location when data is swapped in at that location.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Baskakov et al. and Shultz et al. to include pausing and resuming operation, as taught by Schlansker et al., in order to improve data integrity by ensuring that the correct pages are accessed.
Claim 11 (as applied to claim 8 above):
Claim 11, directed to a method, is rejected for the same reasons set forth in the rejection of claim 4 above, mutatis mutandis.
Claim 18 (as applied to claim 15 above):
Claim 18, directed to a non-transitory computer-readable medium, is rejected for the same reasons set forth in the rejection of claim 4 above, mutatis mutandis.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baskakov et al. (Pub. No. US 2015/0309736) in view of Shultz et al. (Pub. No. US 2009/0006801) as applied to claim 1 and 8 above, respectively, and further in view of Mehra et al. (Pub. No. US 2018/0121121).
Claim 7 (as applied to claim 1 above):
Baskakov et al. and Shultz et al. disclose all the limitations above but do not specifically disclose, wherein the one or more controllers are further configured to cause the apparatus to:
transfer, from an area of a cache in one or more controllers, cursor information for the second type of write operation to the non-volatile memory; and
write address mapping information to the area of the cache based at least in part on transferring the cursor information for the second type of write operation from the area.
In the same field of endeavor, Mehra et al. disclose the apparatus to:
transfer, from an area of a cache in one or more controllers, cursor information for the second type of write operation to the non-volatile memory [figs. 20-22; pars. 0117-0118 – L2P entries are evicted. (“In device-based FTL implementations, the data manipulation instructions specify one or more logical addresses corresponding to the data on which the data manipulation operations are to be performed. In some embodiments, in response to receiving the data manipulation instructions, the controller determines one or more relevant L2P entries associated with the one or more logical addresses used by the data manipulation instructions (e.g., corresponding to the data to be processed). In some embodiments, the relevant L2P entries (e.g., those used by the data manipulation instructions) are a subset of the L2P entries in the address translation table. In some embodiments, the controller retains the relevant L2P entries in local memory and evicts from local memory (or otherwise ceases to store in local memory) at least a subset of the L2P entries not specified or not used by the data manipulation instructions.”)]; and
write address mapping information to the area of the cache based at least in part on transferring the cursor information for the second type of write operation from the area [figs. 20-22; pars. 0117-0118 – L2P entries are cached. (“In device-based FTL implementations, the data manipulation instructions specify one or more logical addresses corresponding to the data on which the data manipulation operations are to be performed. In some embodiments, in response to receiving the data manipulation instructions, the controller determines one or more relevant L2P entries associated with the one or more logical addresses used by the data manipulation instructions (e.g., corresponding to the data to be processed). In some embodiments, the relevant L2P entries (e.g., those used by the data manipulation instructions) are a subset of the L2P entries in the address translation table. In some embodiments, the controller retains the relevant L2P entries in local memory and evicts from local memory (or otherwise ceases to store in local memory) at least a subset of the L2P entries not specified or not used by the data manipulation instructions.”)].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Baskakov et al. and Shultz et al. to include caching l2p entries, as taught by Mehra et al., in order to improve performance.
Claim 14 (as applied to claim 8 above):
Claim 14, directed to a method, is rejected for the same reasons set forth in the rejection of claim 7 above, mutatis mutandis.
Allowable Subject Matter
Claims 5, 6, 12, 13, 19, and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The prior art does not disclose increasing and decreasing a size of a tracking log in conjunction with the other claim language.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
20 June 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139
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