Prosecution Insights
Last updated: October 24, 2026
Application No. 18/625,056

TRAINING METHOD AND APPARATUS FOR CHIP LAYOUT ENCODER AND CHIP LAYOUT SCREENING METHOD AND APPARATUS

Non-Final OA §101§102§103
Filed
Apr 02, 2024
Priority
Sep 26, 2022 — CN 202211176018.8 +2 more
Examiner
LIN, ARIC
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tencent Technology (Shenzhen) Company Limited
OA Round
1 (Non-Final)
59%
Grant Probability
Moderate
1-2
OA Rounds
7m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 59% of resolved cases
59%
Career Allowance Rate
315 granted / 530 resolved
-8.6% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
38 currently pending
Career history
586
Total Applications
across all art units

Statute-Specific Performance

§101
19.0%
-21.0% vs TC avg
§103
44.3%
+4.3% vs TC avg
§102
12.0%
-28.0% vs TC avg
§112
21.4%
-18.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 530 resolved cases

Office Action

§101 §102 §103
DETAILED ACTION This office action is in response to Application No. 18/625,056, filed on 2 April 2024. Claims 1-18 are pending. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-5, 7-11, and 13-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract mental processes without significantly more. The claim(s) recite(s) extracting layout features, clustering the layouts based on the features, and identifying a key layout from the layout groups, which is an abstract mental process that could be performed by humans in the mind or with pen and paper by identifying salient features, clustering layouts based on those features, and selecting layouts from the clusters. Claims 2-4 recite a mathematical algorithm for clustering (the recited steps describe, e.g., k-means clustering). Claim 5 recites evenly sampling from the cluster based on distance, which is another abstract mental step could be performed by a human. Claims 7-11 and 13-17 are analogous to claims 1-5. This judicial exception is not integrated into a practical application because aside from the abstract idea itself, the claims recite merely generic computer implementation, which does not qualify as integration into a patentable practical application. Even in its narrowest reading, the claims would only apply generic machine learning techniques to the field of layout, similar to the claims found ineligible in Recentive Analytics, Inc. v. Fox Corp, 134 F.4th 1205. For the same reasons, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 7, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cecil (US 2020/0372365). Regarding claim 1, Cecil discloses a chip layout screening method performed by an electronic device (Fig. 9; ¶22), the method comprising: extracting target layout features of a plurality of target chip layouts by using a chip layout encoder (¶¶4, 39); performing clustering on the plurality of target chip layouts based on the target layout features to obtain a plurality of target clusters, wherein each target cluster comprises a group of target chip layouts (¶¶41, 64); and identifying a key chip layout from a respective group of target chip layouts (¶¶4, 41). Claim 7 and 13 are directed to an electronic device comprising a processor and memory, and a non-transitory computer-readable storage medium, for performing the method of claim 1, and are rejected under similar reasoning. Cecil to an electronic device comprising a processor and memory, and a non-transitory computer-readable storage medium, for performing the claimed method (Fig. 9). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-4, 8-10, and 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by Cecil or, in the alternative, under 35 U.S.C. 103 as obvious over Cecil in view of Chen (US 2022/0100935). Regarding claims 2, 8, and 14, Cecil discloses that the performing clustering on the plurality of target chip layouts based on the target layout features to obtain a plurality of target clusters comprises: obtaining a plurality of first layout features; calculating distances between the target layout features of the plurality of target chip layouts and each first layout feature of the plurality of first layout features; and for a target chip layout, clustering the target chip layout to a first cluster (¶64; k-means clustering works by minimizing the distance between the cluster members and the center). If Cecil is found to be unclear regarding k-means clustering disclosing the claim limitations, Chen discloses the same (¶101). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Cecil and Chen, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using conventional clustering algorithms to group similar patterns for selection of representative subsets. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Cecil discloses clustering layouts using k-means clustering and selecting representative subsets from the clusters. Chen provides explicit details of k-means clustering, and also disclosing using clustering for selecting representative subsets. The teachings of Chen are directly applicable to Cecil in the same way, so that Cecil would similarly use conventional k-means clustering algorithms to cluster layouts for representative subset selection. Regarding claims 3, 9, and 15, Cecil discloses that each first layout feature represents a center of a corresponding one of the plurality of target clusters (¶64; k-means clustering works by minimizing the distance between the cluster members and the center). If Cecil is found to be unclear regarding k-means clustering disclosing the claim limitations, Chen discloses the same (¶101). Motivation to combine remains consistent with claim 2. Regarding claims 4, 10, and 16, Cecil discloses that a distance between a target layout feature of the target chip layout and the first layout feature of the first cluster is a minimum among distances between the target layout feature of the target chip layout and the plurality of first layout features (¶64; k-means clustering works by minimizing the distance between the cluster members and the center). If Cecil is found to be unclear regarding k-means clustering disclosing the claim limitations, Chen discloses the same (¶101). Motivation to combine remains consistent with claim 2. Claim(s) 5, 11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cecil in view of Bachem (“Practical Coreset Constructions for Machine Learning”). Regarding claims 5, 11, and 17, Cecil does not appear to explicitly disclose that the identifying a key chip layout from a respective group of target chip layouts comprises: obtaining distances between layout features of the target chip layouts in the group and a clustering center of a target cluster corresponding to the group of target chip layouts; and evenly sampling the target chip layouts in the group to obtain a plurality of key chip layouts based on the distances between the layout features of the target chip layouts in the group and the clustering center of the target cluster corresponding to the group of target chip layouts. Bachem discloses these limitations (p. 20, ‘Random Sampling’ section). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Cecil and Bachem, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of sampling a representative subset of layouts. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Cecil discloses clustering and selection of a subset of layouts. Bachem teaches that the selection is performed uniformly based on distances from the cluster center. The teachings of Bachem are directly applicable to Cecil in the same way, so that Cecil would similarly perform uniform sampling based on distances from cluster centers to select a representative subset of layouts. Claim(s) 6, 12, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cecil in view of Chen and Liu (US 2011/0099526). Regarding claim 6, 12, and 18, Cecil does not appear to explicitly disclose performing source mask optimization (SMO) on the key chip layout to obtain a target source and a mask layout corresponding to the key chip layout; and performing mask optimization on another chip layout based on the target source, to obtain a mask layout corresponding to the another chip layout, the another chip layout being a target chip layout other than the key chip layout in the target chip layouts. Chen discloses performing source mask optimization on the key chip layout to obtain a target source and a mask layout corresponding to the key chip layout (¶¶9, 87). Liu discloses performing source mask optimization on the key chip layout to obtain a target source and a mask layout corresponding to the key chip layout (¶¶58-60); and performing mask optimization on another chip layout based on the target source, to obtain a mask layout corresponding to the another chip layout, the another chip layout being a target chip layout other than the key chip layout in the target chip layouts (¶61). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Cecil, Chen, and Liu, because doing so would have involved merely the routine combination of known elements according to known techniques, or the routine use of a known technique to improve similar devices in the same way, to produce merely the predictable results of correcting selected layouts. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395-1396. Cecil discloses layout clustering and selection to produce data for models. Chen teaches that the clustering and selection produces data for models for SMO and layout correction. Liu teaches using performing SMO on the selected layouts and layout corrections on the selected and additional layouts. The teachings of Chen and Liu are directly applicable to Cecil in the same way, so that Cecil would similarly select layouts for SMO and layout correction, in order to produce corrected layouts. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIC LIN whose telephone number is (571)270-3090. The examiner can normally be reached M-F 07:30-17:00 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. 28 September 2026 /ARIC LIN/ Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Apr 02, 2024
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §101, §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
59%
Grant Probability
72%
With Interview (+12.1%)
3y 1m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 530 resolved cases by this examiner. Grant probability derived from career allowance rate.

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