DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 21-40 are pending.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 04/02/2024, 07/31/2024 and 05/29/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Drawings
4. Figures 1-6 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 21-25, 27 and 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Booth et al. (US Patent No. 9,213,396 hereinafter “Booth” – IDS Submission) in view of Trauth et al. (US Pub. No. 2016/0026203 A1 hereinafter “Trauth” – IDS Submission).
Referring to claim 21, Booth discloses the peripheral device (Booth – Col. 3, lines 8-9 discloses a first module 104 as a I2C slave.) comprising:
a terminal (Booth – Figs. 1 and 2 having a power connection 112.) having an external resistor connected thereto and that is external to the peripheral device (Booth – Figs. 1, 2 & col. 4, lines 37-38 disclosing the power connection 112 is coupled to a resistor divider made of resistor 208 and resistor 210. Col. 4, lines 60-62 discloses the resistor divider may be integrated into the IC package instead of internal to the first module 104. This implies that resistors 208/210 may alternatively be located outside of the toner bottle 105 and first module 104.);
a detection circuit configured to determine an enumeration value corresponding to a device address of the peripheral device, the enumeration value determined based at least in part on a voltage detected across the external resistor, and the enumeration value determined independently of signaling from an external controller in communication with the peripheral device (Booth – Col. 3, line 66 to col. 4, line 53 & Fig. 2 disclosing an authentication circuit 202 utilizes the voltage provided by the voltage divider to generate a serial communication address for the authentication circuit 202.); and an address register to store the device address (Booth – Col. 1, lines 36-41 discloses a single color printer, such as a mono printer, may have an authentication circuit on a toner bottle and another authentication circuit on an imaging unit. These modules that contain the authentication circuits may be nearly identical, the only difference being a non-volatile memory variable that contains the module address. Col. 4, lines 54-67 disclosing one or more of these independent bits may be stored in a non-volatile memory located within a module.).
Booth fails to explicitly disclose the voltage generated by a bias current applied to the terminal.
Trauth discloses the voltage generated by a bias current (Trauth – Par. [0054] discloses voltage values are provided at some components of the bias current source 1.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Trauth’s teachings with Booth’s teachings for reducing power consumption without deterioration of the performance of the integrated circuit (Trauth – par. [0024]).
Referring to claim 22, Booth and Trauth disclose the peripheral device of claim 21 wherein the detection circuit is implemented using an analog-to-digital converter (Booth – Col. 4, lines 42-43 discloses within the authentication circuit 202, this input is connected to an analog-to-digital converter (ADC).).
Referring to claim 23, Booth and Trauth disclose the peripheral device of claim 21 wherein the detection circuit is implemented using a flash converter (Trauth – Par. [0005] discloses bias current sources used within flash analog-digital converter (ADC).).
Referring to claim 24, Booth and Trauth disclose the peripheral device of claim 21 wherein the device address uniquely identifies the peripheral device on a bus that is connected to a plurality of peripheral devices (Booth – Col. 1, lines 26-28 discloses an I2C bus has one master device and one or more slave devices. Each slave device has a unique communication address.).
Referring to claim 25, Booth and Trauth disclose the peripheral device of claim 21 wherein the detection circuit is further configured to convert the voltage on the terminal to a digital value indicative of the device address based at least in part on an internal reference voltage generated using an internal reference current that differs from the bias current (Booth – Col. 4, lines 37-56 disclosing the ADC converting the voltage into binary bits set to a serial communication address. The ADC may use the operating voltage source 206 as a voltage reference. Alternatively, the authentication circuit 202 may generate a dedicated voltage reference for the ADC. Col. 7, lines 51-61 66 disclosing an operating voltage source is generated from the power connection. The operating voltage may be generated, for example, by a linear regulator and thus the operating voltage may be at least two hundred millivolts lower than the DC voltage on the power connection. The operating voltage may be regulated to a predetermined value, for example 3.3V, to a predetermined tolerance, say 5%, over a range of operating currents, say 0 mA to 10 mA. At block 704, an authentication circuit is powered from the operating voltage source.).
Referring to claim 27, Booth and Trauth disclose the peripheral device of claim 21 further comprising a current source in electrical communication with the terminal (Booth – Figs. 1 and 2 having a power connection 112.) and configured to generate the bias current (Trauth – Par. [0022] & Fig. 1 disclose a bias current source 1 that generates a bias current Ib.).
Referring to claim 30, Booth discloses an address-based communication system comprising:
a bus configured to enable communication with a plurality of devices (Booth – Fig. 1 shows a system application specific integrated circuit (ASIC) 102 coupled to a first module 104 and to a second module 106 via an I2C bus.);
a first device of the plurality of devices (Booth – Col. 3, lines 8-9 discloses a first module 104 as a I2C slave.), the first device including a first terminal (Booth – Figs. 1 and 2 having a power connection 112.), a first detection circuit (Booth – Fig. 2 disclosing an authentication circuit 202.), and a first address register (Booth – Col. 1, lines 36-41 discloses a single color printer, such as a mono printer, may have an authentication circuit on a toner bottle and another authentication circuit on an imaging unit. These modules that contain the authentication circuits may be nearly identical, the only difference being a non-volatile memory variable that contains the module address. Col. 4, lines 54-67 disclosing one or more of these independent bits may be stored in a non-volatile memory located within a module.), the first terminal (Booth – Figs. 1 and 2 having a power connection 112.) having a first external resistor connected thereto and that is external to the first device (Booth – Figs. 1, 2 & col. 4, lines 37-38 disclosing the power connection 112 is coupled to a resistor divider made of resistor 208 and resistor 210. Col. 4, lines 60-62 discloses the resistor divider may be integrated into the IC package instead of internal to the first module 104. This implies that resistors 208/210 may alternatively be located outside of the toner bottle 105 and first module 104.), the first detection circuit configured to determine a first enumeration value corresponding to a first device address of the first device, the first enumeration value determined based at least in part on a first voltage detected across the first external resistor, and the first enumeration value determined independently of signaling from an external controller in communication with the first device (Booth – Col. 3, line 66 to col. 4, line 53 & Fig. 2 disclosing an authentication circuit 202 utilizes the voltage provided by the voltage divider to generate a serial communication address for the authentication circuit 202.), and the first address register configured to store the first device address (Booth – Col. 1, lines 36-41 discloses a single color printer, such as a mono printer, may have an authentication circuit on a toner bottle and another authentication circuit on an imaging unit. These modules that contain the authentication circuits may be nearly identical, the only difference being a non-volatile memory variable that contains the module address. Col. 4, lines 54-67 disclosing one or more of these independent bits may be stored in a non-volatile memory located within a module.); and
a second device of the plurality of devices (Booth – Col. 3, lines 8-9 discloses a second module 106 as a I2C slave.), the second device including a second terminal (Booth – Fig.1 shows the second module 106 having a power connection 126.), a second detection circuit, and a second address register, the second terminal having a second external resistor connected thereto and that is external to the second device, the second detection circuit configured to determine a second enumeration value corresponding to a second device address of the second device, the second enumeration value determined based at least in part on a second voltage detected across the second external resistor, and the second enumeration value determined independently of signaling from the external controller in communication with the second device, and the second address register configured to store the second device address (Booth – Col. 3, lines 36-37 disclose the first module 104 and the second module 106 are identical. This implies that the component mappings of the first module 104 would be the same for component mappings of the second module 106.).
Booth fails to explicitly disclose the first voltage generated by a first bias current applied to the first terminal; and the second voltage generated by a second bias current applied to the second terminal.
Trauth discloses the voltage generated by a bias current (Trauth – Par. [0054] discloses voltage values are provided at some components of the bias current source 1.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Trauth’s teachings with Booth’s teachings for reducing power consumption without deterioration of the performance of the integrated circuit (Trauth – par. [0024]).
Referring to claim 31, Booth and Trauth disclose the address-based communication system of claim 30 wherein the first detection circuit is implemented using an analog-to-digital converter or a flash converter (Booth – Col. 4, lines 42-43 discloses within the authentication circuit 202, this input is connected to an analog-to-digital converter (ADC).).
Referring to claim 32, Booth and Trauth disclose the address-based communication system of claim 30 wherein the first detection circuit is further configured to convert the first voltage on the first terminal to a digital value indicative of the first device address based at least in part on an internal reference voltage generated using an internal reference current that differs from the first bias current (Booth – Col. 4, lines 37-56 disclosing the ADC converting the voltage into binary bits set to a serial communication address. The ADC may use the operating voltage source 206 as a voltage reference. Alternatively, the authentication circuit 202 may generate a dedicated voltage reference for the ADC. Col. 7, lines 51-61 66 disclosing an operating voltage source is generated from the power connection. The operating voltage may be generated, for example, by a linear regulator and thus the operating voltage may be at least two hundred millivolts lower than the DC voltage on the power connection. The operating voltage may be regulated to a predetermined value, for example 3.3V, to a predetermined tolerance, say 5%, over a range of operating currents, say 0 mA to 10 mA. At block 704, an authentication circuit is powered from the operating voltage source.).
8. Claims 26 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Booth in view of Trauth, and further in view of Davis et al. (US Patent No. 9,214,950 A1 hereinafter “Davis” – IDS Submission).
Referring to claim 26, Booth and Trauth disclose the peripheral device of claim 25, however, fail to explicitly disclose wherein the internal reference current is to maintain the voltage on the terminal at a constant value over temperature and process.
Davis discloses the internal reference current is to maintain the voltage on the terminal at a constant value over temperature and process (Davis – See Abstract, Col. 5, line 31 to col. 6, line 23 & Figs. 3, 4.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Davis’ teachings with Booth and Trauth’s teachings for providing the temperature compensated trim current being fed back into the temperature compensated reference current to produce an adjusted temperature compensated reference current (Davis – Col. 3, lines 12-14).
Referring to claim 33, Booth and Trauth disclose the address-based communication system of claim 32, however, fail to explicitly disclose wherein the internal reference current is to maintain the first voltage on the first terminal at a constant value over temperature and process.
Davis discloses the internal reference current is to maintain the first voltage on the first terminal at a constant value over temperature and process (Davis – See Abstract, Col. 5, line 31 to col. 6, line 23 & Figs. 3, 4.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Davis’ teachings with Booth and Trauth’s teachings for providing the temperature compensated trim current being fed back into the temperature compensated reference current to produce an adjusted temperature compensated reference current (Davis – Col. 3, lines 12-14).
9. Claims 28 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Booth in view of Trauth, and further in view of Richards et al. (US Pub. No. 2009/0031048 A1 hereinafter “Richards” – IDS Submission).
Referring to claim 28, Booth and Trauth disclose the peripheral device of claim 21, however, fail to explicitly disclose wherein the device address is stored in the address register responsive to a power on condition or a reset condition.
Richards discloses the device address is stored in the address register responsive to a power on condition or a reset condition (Richards – Par. [0026] discloses a three-bit binary address stored in an address register 112 after a power-on-reset (POR) event.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Richards’ teachings with Booth and Trauth’s teachings for providing a way to program a multi-bit unique address into a device by using a single external connection (pin) on the integrated circuit package of the device (Richards – par. [0005]).
Referring to claim 29, Booth and Trauth disclose the peripheral device of claim 21, however, fail to explicitly disclose wherein the detection circuit is further configured to determine the device address by accessing a lookup table configured to store a mapping between enumeration values and device address values.
Richards discloses the detection circuit is further configured to determine the device address by accessing a lookup table configured to store a mapping between enumeration values and device address values (Richards – Par. [0033] discloses FIG. 4 depicting tables of reference voltages and address voltage ranges for different power supply voltages, and respective flash ADC outputs and three-bit binary addresses.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Richards’ teachings with Booth and Trauth’s teachings for providing a way to program a multi-bit unique address into a device by using a single external connection (pin) on the integrated circuit package of the device (Richard – par. [0005]).
10. Claims 34, 35 and 37-39 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. No. 2021/0119627 A1 hereinafter “Lee” – IDS Submission) in view of Booth, and further in view of Trauth.
Referring to claim 34, Lee discloses the traction inverter system (Lee – Fig. 1 shows a high-voltage power electronics system 100 having a high voltage traction inverter 116.) comprising:
a motor (Lee – Par. [0039] discloses the motor 118 is a three-phase electric motor.).
Lee fails to explicitly disclose a plurality of peripheral devices configured to control the motor, each of the plurality of peripheral devices including a terminal, a detection circuit, and an address register, the terminal having an external resistor connected thereto and that is external to the peripheral device, the detection circuit configured to determine an enumeration value corresponding to a device address of the peripheral device, the enumeration value determined based at least in part on a voltage detected across the external resistor, the voltage generated by a bias current applied to the terminal, and the enumeration value determined independently of signaling from an external controller in communication with the peripheral device, and the address register configured to store the device address; and a controller configured to communicate with the plurality of peripheral devices over a bus to control the plurality of peripheral devices.
Booth discloses a plurality of peripheral devices (Booth – Col. 3, lines 8-9 discloses the first module 104 and the second module 106 are I2C slaves.), each of the plurality of peripheral devices including a terminal (Booth – Fig.1 shows the first module 104 and the second module 106 having a power connection 112, 126 respectfully.), a detection circuit (Booth – Fig. 2 disclosing an authentication circuit 202.), and an address register (Booth – Col. 1, lines 36-41 discloses a single color printer, such as a mono printer, may have an authentication circuit on a toner bottle and another authentication circuit on an imaging unit. These modules that contain the authentication circuits may be nearly identical, the only difference being a non-volatile memory variable that contains the module address. Col. 4, lines 54-67 disclosing one or more of these independent bits may be stored in a non-volatile memory located within a module.), the terminal (Booth – Figs. 1 and 2 having a power connection 112.) having an external resistor connected thereto and that is external to the peripheral device (Booth – Figs. 1, 2 & col. 4, lines 37-38 disclosing the power connection 112 is coupled to a resistor divider made of resistor 208 and resistor 210. Col. 4, lines 60-62 discloses the resistor divider may be integrated into the IC package instead of internal to the first module 104. This implies that resistors 208/210 may alternatively be located outside of the toner bottle 105 and first module 104.), the detection circuit configured to determine an enumeration value corresponding to a device address of the peripheral device, the enumeration value determined based at least in part on a voltage detected across the external resistor, and the enumeration value determined independently of signaling from an external controller in communication with the peripheral device (Booth – Col. 3, line 66 to col. 4, line 53 & Fig. 2 disclosing an authentication circuit 202 utilizes the voltage provided by the voltage divider to generate a serial communication address for the authentication circuit 202.), and the address register configured to store the device address (Booth – Col. 1, lines 36-41 discloses a single color printer, such as a mono printer, may have an authentication circuit on a toner bottle and another authentication circuit on an imaging unit. These modules that contain the authentication circuits may be nearly identical, the only difference being a non-volatile memory variable that contains the module address. Col. 4, lines 54-67 disclosing one or more of these independent bits may be stored in a non-volatile memory located within a module.); and
a controller configured to communicate with the plurality of peripheral devices over a bus to control the plurality of peripheral devices (Booth – Fig. 1 shows a system application specific integrated circuit (ASIC) 102 coupled to a first module 104 and to a second module 106 via an I2C bus.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Booth teachings with Lee’s teachings for providing a system having two identical modules on the same I2C bus but at different addresses, and this function is provided without adding additional connections which allows identical modules to be populated into multiple system components, which simplifies manufacturing and lowers cost (Booth – Col. 3, lines 53-58).
Lee and Booth fails to explicitly disclose the voltage generated by a bias current applied to the terminal.
Trauth discloses the voltage generated by a bias current (Trauth – Par. [0054] discloses voltage values are provided at some components of the bias current source 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Trauth’s teachings with Lee and Booth’s teachings for reducing power consumption without deterioration of the performance of the integrated circuit (Trauth – par. [0024]).
Referring to claim 35, Lee, Booth and Trauth disclose the traction inverter system of claim 34 wherein the motor is a three phase high voltage motor (Lee – Par. [0039] discloses the motor 118 is a three-phase electric motor.).
Referring to claim 37, Lee, Booth and Trauth disclose the traction inverter system of claim 34 wherein the detection circuit of each peripheral device of the plurality of peripheral devices is implemented using an analog-to-digital converter or a flash converter (Booth – Col. 4, lines 42-43 discloses within the authentication circuit 202, this input is connected to an analog-to-digital converter (ADC).).
Referring to claim 38, Lee, Booth and Trauth disclose the traction inverter system of claim 34 wherein the device address of each peripheral device of the plurality of peripheral devices uniquely identifies the peripheral device on the bus enabling the controller to communicate with a selected peripheral device (Booth – Col. 1, lines 26-28 discloses an I2C bus has one master device and one or more slave devices. Each slave device has a unique communication address so that the master device can direct communication to a particular slave device.).
Referring to claim 39, Lee, Booth and Trauth disclose the traction inverter system of claim 34 wherein the detection circuit of each peripheral device of the plurality of peripheral devices is further configured to convert the voltage on the terminal of the peripheral device to a digital value indicative of the device address based at least in part on an internal reference voltage generated using an internal reference current that differs from the bias current (Booth – Col. 4, lines 37-56 disclosing the ADC converting the voltage into binary bits set to a serial communication address. The ADC may use the operating voltage source 206 as a voltage reference. Alternatively, the authentication circuit 202 may generate a dedicated voltage reference for the ADC. Col. 7, lines 51-61 66 disclosing an operating voltage source is generated from the power connection. The operating voltage may be generated, for example, by a linear regulator and thus the operating voltage may be at least two hundred millivolts lower than the DC voltage on the power connection. The operating voltage may be regulated to a predetermined value, for example 3.3V, to a predetermined tolerance, say 5%, over a range of operating currents, say 0 mA to 10 mA. At block 704, an authentication circuit is powered from the operating voltage source.).
11. Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Booth and Trauth, and further in view of Kirby et al. (US Pub. No. 2021/0305927 hereinafter “Kirby”).
Referring to claim 36, Lee, Booth and Trauth disclose the traction inverter system of claim 34, however, fail to explicitly disclose wherein the controller comprises a processor configured to operate in a first voltage domain that is at least a magnitude less than a second voltage domain, and the motor is configured to operate in the second voltage domain.
Kirby discloses the controller comprises a processor configured to operate in a first voltage domain that is at least a magnitude less than a second voltage domain, and the motor is configured to operate in the second voltage domain (Kirby – Par. [0016] discloses a processor 100 operates in a first voltage domain (i.e., VDD1, e.g., 5V) and provides one or more signals for a high power load system operating in a second voltage domain (i.e., VDD3, e.g., hundreds of volts). Par. [0004] discloses the motor 120 operates in the second doman VDD3.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Kirby’s teachings with Lee, Booth and Trauth’s teachings for providing flexible techniques for handling fault conditions without damaging high-power drive devices or the load that those devices control (Kirby – Par. [0004]).
12. Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Booth and Trauth, and further in view of Davis.
Referring to claim 40, Lee, Booth and Trauth disclose the traction inverter system of claim 39, however, fail to explicitly disclose wherein the internal reference current is to maintain the voltage on the terminal at a constant value over temperature and process.
Davis discloses the internal reference current is to maintain the voltage on the terminal at a constant value over temperature and process (Davis – See Abstract, Col. 5, line 31 to col. 6, line 23 & Figs. 3, 4.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Davis’ teachings with Lee, Booth and Trauth’s teachings for providing the temperature compensated trim current being fed back into the temperature compensated reference current to produce an adjusted temperature compensated reference current (Davis – Col. 3, lines 12-14).
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Ill(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 2707754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
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/Dayton Lewis-Taylor/
Examiner, Art Unit 2181